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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id q26sm5114308wmq.25.2019.05.10.09.49.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 10 May 2019 09:49:48 -0700 (PDT) From: Jerome Brunet To: Kevin Hilman Subject: [PATCH 4/5] arm64: dts: meson: u200: add internal network Date: Fri, 10 May 2019 18:49:39 +0200 Message-Id: <20190510164940.13496-5-jbrunet@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190510164940.13496-1-jbrunet@baylibre.com> References: <20190510164940.13496-1-jbrunet@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190510_094950_733687_986FE972 X-CRM114-Status: UNSURE ( 9.26 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The u200 is the main mother board for the S905D2. It can provide both the internal and external network. However, by default the resistance required for the external RGMII bus are not fitted, so enable the internal PHY. Signed-off-by: Jerome Brunet --- arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts index 7cc3e2d6a4f1..c2221eb4549e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts @@ -15,6 +15,7 @@ aliases { serial0 = &uart_AO; + ethernet0 = ðmac; }; chosen { @@ -145,6 +146,12 @@ }; }; +ðmac { + status = "okay"; + phy-handle = <&internal_ephy>; + phy-mode = "rmii"; +}; + &hdmi_tx { status = "okay"; pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;