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[2003:f1:33dd:a400:b42d:8eb9:d711:c35e]) by smtp.googlemail.com with ESMTPSA id h14sm2007731wrs.66.2019.06.09.11.06.41 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sun, 09 Jun 2019 11:06:41 -0700 (PDT) From: Martin Blumenstingl To: netdev@vger.kernel.org, linux-gpio@vger.kernel.org, linux-amlogic@lists.infradead.org, linus.walleij@linaro.org, bgolaszewski@baylibre.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, joabreu@synopsys.com Subject: [RFC next v1 5/5] arm64: dts: meson: g12a: x96-max: fix the Ethernet PHY reset line Date: Sun, 9 Jun 2019 20:06:21 +0200 Message-Id: <20190609180621.7607-6-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190609180621.7607-1-martin.blumenstingl@googlemail.com> References: <20190609180621.7607-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190609_110644_999334_EEFE2AAA X-CRM114-Status: GOOD ( 13.27 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, narmstrong@baylibre.com, Martin Blumenstingl , khilman@baylibre.com, linux-kernel@vger.kernel.org, davem@davemloft.net, linux-arm-kernel@lists.infradead.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The PHY reset line and interrupt line are swapped on the X96 Max compared to the Odroid-N2 schematics. This means: - GPIOZ_14 is the interrupt line (on the Odroid-N2 it's the reset line) - GPIOZ_15 is the reset line (on the Odroid-N2 it's the interrupt line) Also the GPIOZ_14 and GPIOZ_15 pins are special. The datasheet describes that they are "3.3V input tolerant open drain (OD) output pins". This means the GPIO controller can drive the output LOW to reset the PHY. To release the reset it can only switch the pin to input mode. The output cannot be driven HIGH for these pins. This requires configuring the reset line as GPIO_OPEN_SOURCE because otherwise the PHY will be stuck in "reset" state (because driving the pin HIGH seeems to result in the same signal as driving it LOW). Switch to GPIOZ_15 for the reset GPIO with the correct flags and drop the "snps,reset-active-low" property as this is now encoded in the GPIO_OPEN_SOURCE flag. Fixes: 51d116557b2044 ("arm64: dts: meson-g12a-x96-max: Add Gigabit Ethernet Support") Signed-off-by: Martin Blumenstingl Reviewed-by: Linus Walleij --- arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts index 98bc56e650a0..c93b639679c0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts @@ -186,9 +186,8 @@ phy-mode = "rgmii"; phy-handle = <&external_phy>; amlogic,tx-delay-ns = <2>; - snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-gpio = <&gpio GPIOZ_15 GPIO_OPEN_SOURCE>; snps,reset-delays-us = <0 10000 1000000>; - snps,reset-active-low; }; &pwm_ef {