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[2003:f1:3710:ed00:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id b187sm1260509wmc.14.2020.03.30.15.11.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Mar 2020 15:11:28 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, khilman@baylibre.com, jbrunet@baylibre.com, narmstrong@baylibre.com Subject: [RFC v1 1/5] clk: meson: gxbb: Prepare the GPU clock tree to change at runtime Date: Tue, 31 Mar 2020 00:11:00 +0200 Message-Id: <20200330221104.3163788-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200330221104.3163788-1-martin.blumenstingl@googlemail.com> References: <20200330221104.3163788-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200330_151131_330891_E5968C1F X-CRM114-Status: GOOD ( 14.10 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:442 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [martin.blumenstingl[at]googlemail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Martin Blumenstingl , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org The "mali_0" or "mali_1" clock trees should not be updated while the clock is running. Enforce this by setting CLK_SET_RATE_GATE on the "mali_0" and "mali_1" gates. This makes the CCF switch to the "mali_1" tree when "mali_0" is currently active and vice versa, which is exactly what the vendor driver does when updating the frequency of the mali clock. Also populate set_rate requests from the divider to the mux so the GPU clock frequency can be updated at runtime (which will be required for GPU DVFS). Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/gxbb.c | 40 ++++++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 18 deletions(-) diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 5fd6a574f8c3..0a68af6eec3d 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -957,7 +957,9 @@ static struct clk_regmap gxbb_sar_adc_clk = { /* * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) - * muxed by a glitch-free switch. + * muxed by a glitch-free switch. The CCF can manage this glitch-free + * mux because it does top-to-bottom updates the each clock tree and + * switches to the "inactive" one when CLK_SET_RATE_GATE is set. */ static const struct clk_parent_data gxbb_mali_0_1_parent_data[] = { @@ -980,14 +982,15 @@ static struct clk_regmap gxbb_mali_0_sel = { .hw.init = &(struct clk_init_data){ .name = "mali_0_sel", .ops = &clk_regmap_mux_ops, - /* - * bits 10:9 selects from 8 possible parents: - * xtal, gp0_pll, mpll2, mpll1, fclk_div7, - * fclk_div4, fclk_div3, fclk_div5 - */ .parent_data = gxbb_mali_0_1_parent_data, .num_parents = 8, - .flags = CLK_SET_RATE_NO_REPARENT, + /* + * Don't request the parent to change the rate because + * all GPU frequencies can be derived from the fclk_* + * clocks and one special GP0_PLL setting. This is + * important because we need the MPLL clocks for audio. + */ + .flags = 0, }, }; @@ -1004,7 +1007,7 @@ static struct clk_regmap gxbb_mali_0_div = { &gxbb_mali_0_sel.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_NO_REPARENT, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -1020,7 +1023,7 @@ static struct clk_regmap gxbb_mali_0 = { &gxbb_mali_0_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, }, }; @@ -1033,14 +1036,15 @@ static struct clk_regmap gxbb_mali_1_sel = { .hw.init = &(struct clk_init_data){ .name = "mali_1_sel", .ops = &clk_regmap_mux_ops, - /* - * bits 10:9 selects from 8 possible parents: - * xtal, gp0_pll, mpll2, mpll1, fclk_div7, - * fclk_div4, fclk_div3, fclk_div5 - */ .parent_data = gxbb_mali_0_1_parent_data, .num_parents = 8, - .flags = CLK_SET_RATE_NO_REPARENT, + /* + * Don't request the parent to change the rate because + * all GPU frequencies can be derived from the fclk_* + * clocks and one special GP0_PLL setting. This is + * important because we need the MPLL clocks for audio. + */ + .flags = 0, }, }; @@ -1057,7 +1061,7 @@ static struct clk_regmap gxbb_mali_1_div = { &gxbb_mali_1_sel.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_NO_REPARENT, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -1073,7 +1077,7 @@ static struct clk_regmap gxbb_mali_1 = { &gxbb_mali_1_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, }, }; @@ -1093,7 +1097,7 @@ static struct clk_regmap gxbb_mali = { .ops = &clk_regmap_mux_ops, .parent_hws = gxbb_mali_parent_hws, .num_parents = 2, - .flags = CLK_SET_RATE_NO_REPARENT, + .flags = CLK_SET_RATE_PARENT, }, };