| Message ID | 20200618095150.GA9713@home-desktop (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: dts: odroid: add spicc0 controller node | expand |
Hi, On 18/06/2020 11:51, Hyeonki Hong wrote: > Add enabled spicc0 controller node with annotations describing the > physical SPI0 pin number based on the 40 pin header on the Odroid > board. Thanks for the patch, but unfortunately this enables SPICC on the 40pin headers, and since these pins can be used in various ways this doesn't match the upstream device tree policy. This should be used as a DT overlay instead. > > Signed-off-by: Hyeonki Hong <hhk7734@gmail.com> > --- > .../boot/dts/amlogic/meson-g12b-odroid-n2.dts | 26 +++++++++++++++++-- > .../boot/dts/amlogic/meson-sm1-odroid-c4.dts | 24 ++++++++++++++++- > 2 files changed, 47 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts > index 169ea283d4ee..ec6d345caaae 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts > +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts > @@ -16,8 +16,9 @@ > model = "Hardkernel ODROID-N2"; > > aliases { > - serial0 = &uart_AO; > ethernet0 = ðmac; > + serial0 = &uart_AO; > + spi0 = &spicc0 > }; > > chosen { > @@ -328,7 +329,7 @@ > > &ext_mdio { > external_phy: ethernet-phy@0 { > - /* Realtek RTL8211F (0x001cc916) */ > + /* Realtek RTL8211F (0x001cc916) */ > reg = <0>; > max-speed = <1000>; > > @@ -451,6 +452,27 @@ > vqmmc-supply = <&flash_1v8>; > }; > > +&spicc0 { > + status = "okay"; > + > + /* > + * 40 Pin Header : MOSI(GPIOX.8->19 Pin), > + * MISO(GPIOX.9->21 Pin), > + * SPI0_CLK(GPIOX.11->23 Pin) > + * SPI_CE0(GPIOX.10->24 Pin), > + */ > + pinctrl-names = "default"; > + pinctrl-0 = <&spicc0_x_pins>, <&spicc0_ss0_x_pins>; > + > + spidev@0 { > + compatible = "spidev"; spidev alone is not allowed either, since there is no true fixed devices here. > + status = "okay"; > + /* spi default max clock 100Mhz */ > + spi-max-frequency = <100000000>; > + reg = <0>; > + }; > +}; > + > /* > * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR pins > * and eMMC Data 4 to 7 pins. > diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts > index 00d90b30f8b4..f809b2ba6b15 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts > +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts > @@ -14,8 +14,9 @@ > model = "Hardkernel ODROID-C4"; > > aliases { > - serial0 = &uart_AO; > ethernet0 = ðmac; > + serial0 = &uart_AO; > + spi0 = &spicc0; > }; > > chosen { > @@ -381,6 +382,27 @@ > vqmmc-supply = <&flash_1v8>; > }; > > +&spicc0 { > + status = "okay"; > + > + /* > + * 40 Pin Header : MOSI(GPIOX.8->19 Pin), > + * MISO(GPIOX.9->21 Pin), > + * SPI0_CLK(GPIOX.11->23 Pin) > + * SPI_CE0(GPIOX.10->24 Pin), > + */ > + pinctrl-names = "default"; > + pinctrl-0 = <&spicc0_x_pins>, <&spicc0_ss0_x_pins>; > + > + spidev@0 { > + compatible = "spidev"; > + status = "okay"; > + /* spi default max clock 100Mhz */ > + spi-max-frequency = <100000000>; > + reg = <0>; > + }; > +}; > + > &uart_AO { > status = "okay"; > pinctrl-0 = <&uart_ao_a_pins>; > Thanks, Neil
Hi Hyeonki,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on v5.8-rc1 next-20200618]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Hyeonki-Hong/arm64-dts-odroid-add-spicc0-controller-node/20200618-175307
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts:22.2-3 syntax error
>> FATAL ERROR: Unable to parse input tree
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts index 169ea283d4ee..ec6d345caaae 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts @@ -16,8 +16,9 @@ model = "Hardkernel ODROID-N2"; aliases { - serial0 = &uart_AO; ethernet0 = ðmac; + serial0 = &uart_AO; + spi0 = &spicc0 }; chosen { @@ -328,7 +329,7 @@ &ext_mdio { external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ + /* Realtek RTL8211F (0x001cc916) */ reg = <0>; max-speed = <1000>; @@ -451,6 +452,27 @@ vqmmc-supply = <&flash_1v8>; }; +&spicc0 { + status = "okay"; + + /* + * 40 Pin Header : MOSI(GPIOX.8->19 Pin), + * MISO(GPIOX.9->21 Pin), + * SPI0_CLK(GPIOX.11->23 Pin) + * SPI_CE0(GPIOX.10->24 Pin), + */ + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_x_pins>, <&spicc0_ss0_x_pins>; + + spidev@0 { + compatible = "spidev"; + status = "okay"; + /* spi default max clock 100Mhz */ + spi-max-frequency = <100000000>; + reg = <0>; + }; +}; + /* * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR pins * and eMMC Data 4 to 7 pins. diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts index 00d90b30f8b4..f809b2ba6b15 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts @@ -14,8 +14,9 @@ model = "Hardkernel ODROID-C4"; aliases { - serial0 = &uart_AO; ethernet0 = ðmac; + serial0 = &uart_AO; + spi0 = &spicc0; }; chosen { @@ -381,6 +382,27 @@ vqmmc-supply = <&flash_1v8>; }; +&spicc0 { + status = "okay"; + + /* + * 40 Pin Header : MOSI(GPIOX.8->19 Pin), + * MISO(GPIOX.9->21 Pin), + * SPI0_CLK(GPIOX.11->23 Pin) + * SPI_CE0(GPIOX.10->24 Pin), + */ + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_x_pins>, <&spicc0_ss0_x_pins>; + + spidev@0 { + compatible = "spidev"; + status = "okay"; + /* spi default max clock 100Mhz */ + spi-max-frequency = <100000000>; + reg = <0>; + }; +}; + &uart_AO { status = "okay"; pinctrl-0 = <&uart_ao_a_pins>;
Add enabled spicc0 controller node with annotations describing the physical SPI0 pin number based on the 40 pin header on the Odroid board. Signed-off-by: Hyeonki Hong <hhk7734@gmail.com> --- .../boot/dts/amlogic/meson-g12b-odroid-n2.dts | 26 +++++++++++++++++-- .../boot/dts/amlogic/meson-sm1-odroid-c4.dts | 24 ++++++++++++++++- 2 files changed, 47 insertions(+), 3 deletions(-)