| Message ID | 20200620161422.24114-1-martin.blumenstingl@googlemail.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | d4db5721f3c847df43b967d9f02994b15e4a48e6 |
| Delegated to: | Neil Armstrong |
| Headers | show |
| Series | clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2 | expand |
On 20/06/2020 18:14, Martin Blumenstingl wrote: > Drop CLK_IS_CRITICAL from fclk_div2. This was added because we didn't > know the relation between this clock and RGMII Ethernet. It turns out > that fclk_div2 is used as "timing adjustment clock" to generate the RX > delay on the MAC side - which was enabled by u-boot on Odriod-C1. When > using the RX delay on the PHY side or not using a RX delay at all then > this clock can be disabled. > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > --- > drivers/clk/meson/meson8b.c | 7 ------- > 1 file changed, 7 deletions(-) > > diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c > index edc09d050ecf..3d826711c820 100644 > --- a/drivers/clk/meson/meson8b.c > +++ b/drivers/clk/meson/meson8b.c > @@ -293,13 +293,6 @@ static struct clk_regmap meson8b_fclk_div2 = { > &meson8b_fclk_div2_div.hw > }, > .num_parents = 1, > - /* > - * FIXME: Ethernet with a RGMII PHYs is not working if > - * fclk_div2 is disabled. it is currently unclear why this > - * is. keep it enabled until the Ethernet driver knows how > - * to manage this clock. > - */ > - .flags = CLK_IS_CRITICAL, > }, > }; > > Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
On Sat 20 Jun 2020 at 18:14, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote: > Drop CLK_IS_CRITICAL from fclk_div2. This was added because we didn't > know the relation between this clock and RGMII Ethernet. It turns out > that fclk_div2 is used as "timing adjustment clock" to generate the RX > delay on the MAC side - which was enabled by u-boot on Odriod-C1. When > using the RX delay on the PHY side or not using a RX delay at all then > this clock can be disabled. > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Applied. Thx
Hello: This patch was applied to khilman/linux-amlogic.git (refs/heads/for-next). On Sat, 20 Jun 2020 18:14:22 +0200 you wrote: > Drop CLK_IS_CRITICAL from fclk_div2. This was added because we didn't > know the relation between this clock and RGMII Ethernet. It turns out > that fclk_div2 is used as "timing adjustment clock" to generate the RX > delay on the MAC side - which was enabled by u-boot on Odriod-C1. When > using the RX delay on the PHY side or not using a RX delay at all then > this clock can be disabled. > > [...] Here is a summary with links: - clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2 https://git.kernel.org/khilman/linux-amlogic/c/d4db5721f3c847df43b967d9f02994b15e4a48e6 You are awesome, thank you!
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index edc09d050ecf..3d826711c820 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -293,13 +293,6 @@ static struct clk_regmap meson8b_fclk_div2 = { &meson8b_fclk_div2_div.hw }, .num_parents = 1, - /* - * FIXME: Ethernet with a RGMII PHYs is not working if - * fclk_div2 is disabled. it is currently unclear why this - * is. keep it enabled until the Ethernet driver knows how - * to manage this clock. - */ - .flags = CLK_IS_CRITICAL, }, };
Drop CLK_IS_CRITICAL from fclk_div2. This was added because we didn't know the relation between this clock and RGMII Ethernet. It turns out that fclk_div2 is used as "timing adjustment clock" to generate the RX delay on the MAC side - which was enabled by u-boot on Odriod-C1. When using the RX delay on the PHY side or not using a RX delay at all then this clock can be disabled. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- drivers/clk/meson/meson8b.c | 7 ------- 1 file changed, 7 deletions(-)