| Message ID | 20200908151853.4837-4-narmstrong@baylibre.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Neil Armstrong |
| Headers | show |
| Series | drm/panfrost: add Amlogic integration quirks | expand |
On 08/09/2020 16:18, Neil Armstrong wrote: > The T820, G31 & G52 GPUs integratewd by Amlogic in the respective GXM, G12A/SM1 & G12B > SoCs needs a quirk in the PWR registers at the GPU reset time. > > This adds a callback in the device compatible struct of permit this. > > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- > drivers/gpu/drm/panfrost/panfrost_device.h | 3 +++ > drivers/gpu/drm/panfrost/panfrost_gpu.c | 4 ++++ > 2 files changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h > index 2cf1a6a13af8..4c9cd5452ba5 100644 > --- a/drivers/gpu/drm/panfrost/panfrost_device.h > +++ b/drivers/gpu/drm/panfrost/panfrost_device.h > @@ -73,6 +73,9 @@ struct panfrost_compatible { > > /* IOMMU quirks flags */ > unsigned long pgtbl_quirks; > + > + /* Vendor implementation quirks at reset time callback */ > + void (*vendor_reset_quirk)(struct panfrost_device *pfdev); > }; > > struct panfrost_device { > diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c > index e0f190e43813..c129aaf77790 100644 > --- a/drivers/gpu/drm/panfrost/panfrost_gpu.c > +++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c > @@ -62,6 +62,10 @@ int panfrost_gpu_soft_reset(struct panfrost_device *pfdev) > gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED); > gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET); > > + /* The Amlogic GPU integration needs quirks at this stage */ > + if (pfdev->comp->vendor_reset_quirk) > + pfdev->comp->vendor_reset_quirk(pfdev); > + > ret = readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT, > val, val & GPU_IRQ_RESET_COMPLETED, 100, 10000); Placing the quirk before the reset has completed is dodgy. Can this be ordered after the GPU_IRQ_RESET_COMPLETED signal has been seen? The problem is the reset could (in theory) cause a power transition (e.g. if the GPU is reset while a core is powered) and changing the PWR_OVERRIDEx registers during a transition is undefined. But I don't know the details of how the hardware is broken so it is possible the override is needed for the reset to complete so this would need testing. I also wonder if this could live in panfrost_gpu_init_quirks() instead? Although that is mostly about quirks common to all Mali GPU implementations rather than a specific implementation. Although now I've looked I've noticed we have a bug as we don't appear to reapply those quirks after a reset - I'll send a patch! Steve
On 09/09/2020 14:23, Steven Price wrote: > On 08/09/2020 16:18, Neil Armstrong wrote: >> The T820, G31 & G52 GPUs integratewd by Amlogic in the respective GXM, G12A/SM1 & G12B >> SoCs needs a quirk in the PWR registers at the GPU reset time. >> >> This adds a callback in the device compatible struct of permit this. >> >> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> >> --- >> drivers/gpu/drm/panfrost/panfrost_device.h | 3 +++ >> drivers/gpu/drm/panfrost/panfrost_gpu.c | 4 ++++ >> 2 files changed, 7 insertions(+) >> >> diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h >> index 2cf1a6a13af8..4c9cd5452ba5 100644 >> --- a/drivers/gpu/drm/panfrost/panfrost_device.h >> +++ b/drivers/gpu/drm/panfrost/panfrost_device.h >> @@ -73,6 +73,9 @@ struct panfrost_compatible { >> /* IOMMU quirks flags */ >> unsigned long pgtbl_quirks; >> + >> + /* Vendor implementation quirks at reset time callback */ >> + void (*vendor_reset_quirk)(struct panfrost_device *pfdev); >> }; >> struct panfrost_device { >> diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c >> index e0f190e43813..c129aaf77790 100644 >> --- a/drivers/gpu/drm/panfrost/panfrost_gpu.c >> +++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c >> @@ -62,6 +62,10 @@ int panfrost_gpu_soft_reset(struct panfrost_device *pfdev) >> gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED); >> gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET); >> + /* The Amlogic GPU integration needs quirks at this stage */ >> + if (pfdev->comp->vendor_reset_quirk) >> + pfdev->comp->vendor_reset_quirk(pfdev); >> + >> ret = readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT, >> val, val & GPU_IRQ_RESET_COMPLETED, 100, 10000); > > Placing the quirk before the reset has completed is dodgy. Can this be ordered after the GPU_IRQ_RESET_COMPLETED signal has been seen? The problem is the reset could (in theory) cause a power transition (e.g. if the GPU is reset while a core is powered) and changing the PWR_OVERRIDEx registers during a transition is undefined. But I don't know the details of how the hardware is broken so it is possible the override is needed for the reset to complete so this would need testing. > > I also wonder if this could live in panfrost_gpu_init_quirks() instead? Although that is mostly about quirks common to all Mali GPU implementations rather than a specific implementation. Although now I've looked I've noticed we have a bug as we don't appear to reapply those quirks after a reset - I'll send a patch! Indeed, it needs to be applied after each reset, so if you send a patch for this pretty sure it could live in panfrost_gpu_init_quirks(). Neil > > Steve
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h index 2cf1a6a13af8..4c9cd5452ba5 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.h +++ b/drivers/gpu/drm/panfrost/panfrost_device.h @@ -73,6 +73,9 @@ struct panfrost_compatible { /* IOMMU quirks flags */ unsigned long pgtbl_quirks; + + /* Vendor implementation quirks at reset time callback */ + void (*vendor_reset_quirk)(struct panfrost_device *pfdev); }; struct panfrost_device { diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c index e0f190e43813..c129aaf77790 100644 --- a/drivers/gpu/drm/panfrost/panfrost_gpu.c +++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c @@ -62,6 +62,10 @@ int panfrost_gpu_soft_reset(struct panfrost_device *pfdev) gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED); gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET); + /* The Amlogic GPU integration needs quirks at this stage */ + if (pfdev->comp->vendor_reset_quirk) + pfdev->comp->vendor_reset_quirk(pfdev); + ret = readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT, val, val & GPU_IRQ_RESET_COMPLETED, 100, 10000);
The T820, G31 & G52 GPUs integratewd by Amlogic in the respective GXM, G12A/SM1 & G12B SoCs needs a quirk in the PWR registers at the GPU reset time. This adds a callback in the device compatible struct of permit this. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- drivers/gpu/drm/panfrost/panfrost_device.h | 3 +++ drivers/gpu/drm/panfrost/panfrost_gpu.c | 4 ++++ 2 files changed, 7 insertions(+)