| Message ID | 20210517203724.1006254-2-martin.blumenstingl@googlemail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | clk: meson: rounding for fast clocks on 32-bit SoCs | expand |
On Mon 17 May 2021 at 22:37, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote: > These are useful when running on 32-bit systems to increase the upper > supported frequency limit. clk_ops.round_rate returns a signed long > which limits the maximum rate on 32-bit systems to 2^31 (or approx. > 2.14GHz). clk_ops.determine_rate internally uses an unsigned long so > the maximum rate on 32-bit systems is 2^32 or approx. 4.29GHz. > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > --- > drivers/clk/clk-divider.c | 39 +++++++++++++++++++++++++++++++++++- > include/linux/clk-provider.h | 6 ++++++ > 2 files changed, 44 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c > index 344997203f0e..24c94d2a3643 100644 > --- a/drivers/clk/clk-divider.c > +++ b/drivers/clk/clk-divider.c > @@ -377,7 +377,6 @@ long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, > } > EXPORT_SYMBOL_GPL(divider_ro_round_rate_parent); > > - > static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, > unsigned long *prate) > { > @@ -399,6 +398,44 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, > divider->width, divider->flags); > } > > +int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, > + const struct clk_div_table *table, u8 width, > + unsigned long flags) > +{ > + int div; > + > + div = clk_divider_bestdiv(hw, req->best_parent_hw, req->rate, > + &req->best_parent_rate, table, width, flags); > + > + req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); > + > + return 0; > +} > +EXPORT_SYMBOL_GPL(divider_determine_rate); > + > +int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, > + const struct clk_div_table *table, u8 width, > + unsigned long flags, unsigned int val) > +{ > + int div; > + > + div = _get_div(table, val, flags, width); > + > + /* Even a read-only clock can propagate a rate change */ > + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { > + if (!req->best_parent_hw) > + return -EINVAL; > + > + req->best_parent_rate = clk_hw_round_rate(req->best_parent_hw, > + req->rate * div); > + } > + > + req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); > + > + return 0; > +} > +EXPORT_SYMBOL_GPL(divider_ro_determine_rate); For a final version, could you factorize the code with the .round_rate() variant ? It would remove a bit of duplication. Maybe determine_rate() can also replace round_rate() in the generic divider ops ? > + > int divider_get_val(unsigned long rate, unsigned long parent_rate, > const struct clk_div_table *table, u8 width, > unsigned long flags) > diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h > index 162a2e5546a3..d83b829305c0 100644 > --- a/include/linux/clk-provider.h > +++ b/include/linux/clk-provider.h > @@ -629,6 +629,12 @@ long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, > unsigned long rate, unsigned long *prate, > const struct clk_div_table *table, u8 width, > unsigned long flags, unsigned int val); > +int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, > + const struct clk_div_table *table, u8 width, > + unsigned long flags); > +int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, > + const struct clk_div_table *table, u8 width, > + unsigned long flags, unsigned int val); > int divider_get_val(unsigned long rate, unsigned long parent_rate, > const struct clk_div_table *table, u8 width, > unsigned long flags);
Hi Jerome, On Tue, May 18, 2021 at 9:44 AM Jerome Brunet <jbrunet@baylibre.com> wrote: [...] > > +int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, > > + const struct clk_div_table *table, u8 width, > > + unsigned long flags, unsigned int val) > > +{ > > + int div; > > + > > + div = _get_div(table, val, flags, width); > > + > > + /* Even a read-only clock can propagate a rate change */ > > + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { > > + if (!req->best_parent_hw) > > + return -EINVAL; > > + > > + req->best_parent_rate = clk_hw_round_rate(req->best_parent_hw, > > + req->rate * div); > > + } > > + > > + req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); > > + > > + return 0; > > +} > > +EXPORT_SYMBOL_GPL(divider_ro_determine_rate); > > For a final version, could you factorize the code with the .round_rate() > variant ? It would remove a bit of duplication. my first idea was to basically let the new _determine_rate code just forward all relevant parameters to _round_rate however, I discarded that as it turned out to be less understandable for me as parameters need to be mapped in both ways while writing this mail I noticed that the opposite direction (meaning: _round_rate forwards to _determine_rate) will probably work. I'll give it a try in the next days if you had anything else in mind then please let me know > Maybe determine_rate() can also replace round_rate() in the generic > divider ops ? sure, I'll add that as a separate patch in this series note to myself: testing can be done with the MMC drivers as we're using the generic clk_divider_ops there Best regards, Martin
On Tue 18 May 2021 at 22:33, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote: > Hi Jerome, > > On Tue, May 18, 2021 at 9:44 AM Jerome Brunet <jbrunet@baylibre.com> wrote: > [...] >> > +int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, >> > + const struct clk_div_table *table, u8 width, >> > + unsigned long flags, unsigned int val) >> > +{ >> > + int div; >> > + >> > + div = _get_div(table, val, flags, width); >> > + >> > + /* Even a read-only clock can propagate a rate change */ >> > + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { >> > + if (!req->best_parent_hw) >> > + return -EINVAL; >> > + >> > + req->best_parent_rate = clk_hw_round_rate(req->best_parent_hw, >> > + req->rate * div); >> > + } >> > + >> > + req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); >> > + >> > + return 0; >> > +} >> > +EXPORT_SYMBOL_GPL(divider_ro_determine_rate); >> >> For a final version, could you factorize the code with the .round_rate() >> variant ? It would remove a bit of duplication. > my first idea was to basically let the new _determine_rate code just > forward all relevant parameters to _round_rate > however, I discarded that as it turned out to be less understandable > for me as parameters need to be mapped in both ways > > while writing this mail I noticed that the opposite direction > (meaning: _round_rate forwards to _determine_rate) will probably work. > I'll give it a try in the next days > if you had anything else in mind then please let me know Yep, the idea would be to use the determine_rate() part as the common implementation. AFAICT, all you need is to build req_rate structure in the round_rate() part. > >> Maybe determine_rate() can also replace round_rate() in the generic >> divider ops ? > sure, I'll add that as a separate patch in this series > note to myself: testing can be done with the MMC drivers as we're > using the generic clk_divider_ops there > > > Best regards, > Martin
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 344997203f0e..24c94d2a3643 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -377,7 +377,6 @@ long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, } EXPORT_SYMBOL_GPL(divider_ro_round_rate_parent); - static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { @@ -399,6 +398,44 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, divider->width, divider->flags); } +int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, + const struct clk_div_table *table, u8 width, + unsigned long flags) +{ + int div; + + div = clk_divider_bestdiv(hw, req->best_parent_hw, req->rate, + &req->best_parent_rate, table, width, flags); + + req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); + + return 0; +} +EXPORT_SYMBOL_GPL(divider_determine_rate); + +int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, + const struct clk_div_table *table, u8 width, + unsigned long flags, unsigned int val) +{ + int div; + + div = _get_div(table, val, flags, width); + + /* Even a read-only clock can propagate a rate change */ + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { + if (!req->best_parent_hw) + return -EINVAL; + + req->best_parent_rate = clk_hw_round_rate(req->best_parent_hw, + req->rate * div); + } + + req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); + + return 0; +} +EXPORT_SYMBOL_GPL(divider_ro_determine_rate); + int divider_get_val(unsigned long rate, unsigned long parent_rate, const struct clk_div_table *table, u8 width, unsigned long flags) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 162a2e5546a3..d83b829305c0 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -629,6 +629,12 @@ long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, unsigned long rate, unsigned long *prate, const struct clk_div_table *table, u8 width, unsigned long flags, unsigned int val); +int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, + const struct clk_div_table *table, u8 width, + unsigned long flags); +int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, + const struct clk_div_table *table, u8 width, + unsigned long flags, unsigned int val); int divider_get_val(unsigned long rate, unsigned long parent_rate, const struct clk_div_table *table, u8 width, unsigned long flags);
These are useful when running on 32-bit systems to increase the upper supported frequency limit. clk_ops.round_rate returns a signed long which limits the maximum rate on 32-bit systems to 2^31 (or approx. 2.14GHz). clk_ops.determine_rate internally uses an unsigned long so the maximum rate on 32-bit systems is 2^32 or approx. 4.29GHz. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- drivers/clk/clk-divider.c | 39 +++++++++++++++++++++++++++++++++++- include/linux/clk-provider.h | 6 ++++++ 2 files changed, 44 insertions(+), 1 deletion(-)