| Message ID | 20220118030911.12815-5-yu.tu@amlogic.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Use CCF to describe the UART baud rate clock | expand |
On Tue 18 Jan 2022 at 11:09, Yu Tu <yu.tu@amlogic.com> wrote: > The UART_REG5 register defaults to 0. The console port is set in > ROMCODE. But other UART ports default to 0, so make bit24 and > bit[26,27] writable so that the UART can choose a more > appropriate clock. Suggestion: Instead of talking bits (which is a bit cryptic) tell us what is actually does Something like: Make the internal clock source mux and divider writeable, allowing the uart to deviate from the settings intially applied by the ROMCode and using the most appropriate clocks > > Signed-off-by: Yu Tu <yu.tu@amlogic.com> > --- > drivers/tty/serial/meson_uart.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c > index 92fa91c825e6..4e7b2b38ab0a 100644 > --- a/drivers/tty/serial/meson_uart.c > +++ b/drivers/tty/serial/meson_uart.c > @@ -678,7 +678,7 @@ static int meson_uart_probe_clocks(struct uart_port *port) > CLK_SET_RATE_NO_REPARENT, > port->membase + AML_UART_REG5, > 26, 2, > - CLK_DIVIDER_READ_ONLY, > + CLK_DIVIDER_ROUND_CLOSEST, > xtal_div_table, NULL); > if (IS_ERR(hw)) > return PTR_ERR(hw); > @@ -708,7 +708,7 @@ static int meson_uart_probe_clocks(struct uart_port *port) > CLK_SET_RATE_PARENT, > port->membase + AML_UART_REG5, > 24, 0x1, > - CLK_MUX_READ_ONLY, > + CLK_MUX_ROUND_CLOSEST, > NULL, NULL); > if (IS_ERR(hw)) > return PTR_ERR(hw);
Hi Jerome, Thank you very much for your reply. At present, the problem of switching uART baud rate stuck has been solved. I'm ready to send the next edition. On 2022/1/21 5:49, Jerome Brunet wrote: > [ EXTERNAL EMAIL ] > > > On Tue 18 Jan 2022 at 11:09, Yu Tu <yu.tu@amlogic.com> wrote: > >> The UART_REG5 register defaults to 0. The console port is set in >> ROMCODE. But other UART ports default to 0, so make bit24 and >> bit[26,27] writable so that the UART can choose a more >> appropriate clock. > > Suggestion: Instead of talking bits (which is a bit cryptic) tell us > what is actually does > > Something like: > Make the internal clock source mux and divider writeable, allowing the > uart to deviate from the settings intially applied by the ROMCode and > using the most appropriate clocks > Your description is better, I will follow your suggestion in the next edition. >> >> Signed-off-by: Yu Tu <yu.tu@amlogic.com> >> --- >> drivers/tty/serial/meson_uart.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c >> index 92fa91c825e6..4e7b2b38ab0a 100644 >> --- a/drivers/tty/serial/meson_uart.c >> +++ b/drivers/tty/serial/meson_uart.c >> @@ -678,7 +678,7 @@ static int meson_uart_probe_clocks(struct uart_port *port) >> CLK_SET_RATE_NO_REPARENT, >> port->membase + AML_UART_REG5, >> 26, 2, >> - CLK_DIVIDER_READ_ONLY, >> + CLK_DIVIDER_ROUND_CLOSEST, >> xtal_div_table, NULL); >> if (IS_ERR(hw)) >> return PTR_ERR(hw); >> @@ -708,7 +708,7 @@ static int meson_uart_probe_clocks(struct uart_port *port) >> CLK_SET_RATE_PARENT, >> port->membase + AML_UART_REG5, >> 24, 0x1, >> - CLK_MUX_READ_ONLY, >> + CLK_MUX_ROUND_CLOSEST, >> NULL, NULL); >> if (IS_ERR(hw)) >> return PTR_ERR(hw); >
diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c index 92fa91c825e6..4e7b2b38ab0a 100644 --- a/drivers/tty/serial/meson_uart.c +++ b/drivers/tty/serial/meson_uart.c @@ -678,7 +678,7 @@ static int meson_uart_probe_clocks(struct uart_port *port) CLK_SET_RATE_NO_REPARENT, port->membase + AML_UART_REG5, 26, 2, - CLK_DIVIDER_READ_ONLY, + CLK_DIVIDER_ROUND_CLOSEST, xtal_div_table, NULL); if (IS_ERR(hw)) return PTR_ERR(hw); @@ -708,7 +708,7 @@ static int meson_uart_probe_clocks(struct uart_port *port) CLK_SET_RATE_PARENT, port->membase + AML_UART_REG5, 24, 0x1, - CLK_MUX_READ_ONLY, + CLK_MUX_ROUND_CLOSEST, NULL, NULL); if (IS_ERR(hw)) return PTR_ERR(hw);
The UART_REG5 register defaults to 0. The console port is set in ROMCODE. But other UART ports default to 0, so make bit24 and bit[26,27] writable so that the UART can choose a more appropriate clock. Signed-off-by: Yu Tu <yu.tu@amlogic.com> --- drivers/tty/serial/meson_uart.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)