| Message ID | 20220805085716.5635-6-yu.tu@amlogic.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add S4 SoC PLL and Peripheral clock controller | expand |
On 05/08/2022 10:57, Yu Tu wrote: > Added information about the S4 SOC Peripheral Clock controller in DT. > > Signed-off-by: Yu Tu <yu.tu@amlogic.com> > --- > arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 26 +++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi > index a816b1f7694b..71be1dda15a2 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi > @@ -6,6 +6,8 @@ > #include <dt-bindings/interrupt-controller/irq.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/clock/amlogic,s4-pll-clkc.h> > +#include <dt-bindings/clock/amlogic,s4-clkc.h> > > / { > cpus { > @@ -100,6 +102,30 @@ clkc_pll: pll-clock-controller@8000 { > #clock-cells = <1>; > }; > > + clkc_periphs: periphs-clock-controller { Node names should be generic, so "clock-controller" https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation You miss here unit address. Test your DTS with dtbs check and with regular compile with W=1. Best regards, Krzysztof
Hi Krzysztof,
Thank you for your reply.
On 2022/8/5 17:16, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
>
> On 05/08/2022 10:57, Yu Tu wrote:
>> Added information about the S4 SOC Peripheral Clock controller in DT.
>>
>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>> ---
>> arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 26 +++++++++++++++++++++++
>> 1 file changed, 26 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
>> index a816b1f7694b..71be1dda15a2 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
>> @@ -6,6 +6,8 @@
>> #include <dt-bindings/interrupt-controller/irq.h>
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
>> +#include <dt-bindings/clock/amlogic,s4-clkc.h>
>>
>> / {
>> cpus {
>> @@ -100,6 +102,30 @@ clkc_pll: pll-clock-controller@8000 {
>> #clock-cells = <1>;
>> };
>>
>> + clkc_periphs: periphs-clock-controller {
>
> Node names should be generic, so "clock-controller"
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
>
> You miss here unit address. Test your DTS with dtbs check and with
> regular compile with W=1.
I will change to clkc_periphs: clock-controller@0 {.
Is that okay?
>
>
> Best regards,
> Krzysztof
>
> .
On 05/08/2022 11:36, Yu Tu wrote: >>> @@ -100,6 +102,30 @@ clkc_pll: pll-clock-controller@8000 { >>> #clock-cells = <1>; >>> }; >>> >>> + clkc_periphs: periphs-clock-controller { >> >> Node names should be generic, so "clock-controller" >> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation >> >> You miss here unit address. Test your DTS with dtbs check and with >> regular compile with W=1. > I will change to clkc_periphs: clock-controller@0 {. > Is that okay? I cut the context, so if "0" was the value in reg, then it is OK. Best regards, Krzysztof
On 2022/8/8 14:17, Krzysztof Kozlowski wrote: > [ EXTERNAL EMAIL ] > > On 05/08/2022 11:36, Yu Tu wrote: >>>> @@ -100,6 +102,30 @@ clkc_pll: pll-clock-controller@8000 { >>>> #clock-cells = <1>; >>>> }; >>>> >>>> + clkc_periphs: periphs-clock-controller { >>> >>> Node names should be generic, so "clock-controller" >>> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation >>> >>> You miss here unit address. Test your DTS with dtbs check and with >>> regular compile with W=1. >> I will change to clkc_periphs: clock-controller@0 {. >> Is that okay? > > I cut the context, so if "0" was the value in reg, then it is OK. Ok, I got it.I will change in next version. > Best regards, > Krzysztof > > .
diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi index a816b1f7694b..71be1dda15a2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -6,6 +6,8 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/amlogic,s4-pll-clkc.h> +#include <dt-bindings/clock/amlogic,s4-clkc.h> / { cpus { @@ -100,6 +102,30 @@ clkc_pll: pll-clock-controller@8000 { #clock-cells = <1>; }; + clkc_periphs: periphs-clock-controller { + compatible = "amlogic,s4-periphs-clkc"; + reg = <0x0 0x0 0x0 0x49c>; + clocks = <&clkc_pll CLKID_FCLK_DIV2>, + <&clkc_pll CLKID_FCLK_DIV2P5>, + <&clkc_pll CLKID_FCLK_DIV3>, + <&clkc_pll CLKID_FCLK_DIV4>, + <&clkc_pll CLKID_FCLK_DIV5>, + <&clkc_pll CLKID_FCLK_DIV7>, + <&clkc_pll CLKID_HIFI_PLL>, + <&clkc_pll CLKID_GP0_PLL>, + <&clkc_pll CLKID_MPLL0>, + <&clkc_pll CLKID_MPLL1>, + <&clkc_pll CLKID_MPLL2>, + <&clkc_pll CLKID_MPLL3>, + <&clkc_pll CLKID_HDMI_PLL>, + <&xtal>; + clock-names = "fclk_div2", "fclk_div2p5", "fclk_div3", + "fclk_div4", "fclk_div5", "fclk_div7", + "hifi_pll", "gp0_pll", "mpll0", "mpll1", + "mpll2", "mpll3", "hdmi_pll", "xtal"; + #clock-cells = <1>; + }; + periphs_pinctrl: pinctrl@4000 { compatible = "amlogic,meson-s4-periphs-pinctrl"; #address-cells = <2>;
Added information about the S4 SOC Peripheral Clock controller in DT. Signed-off-by: Yu Tu <yu.tu@amlogic.com> --- arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+)