| Message ID | 20240123165831.970023-3-avromanov@salutedevices.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Support more Amlogic SoC families in crypto driver | expand |
On Tue 23 Jan 2024 at 19:58, Alexey Romanov <avromanov@salutedevices.com> wrote: > Not all Amlogic SoC's uses CLK controller. That's fairly short description and very likely to be wrong. Of all the SoCs I have seen mentionned in the bindings, they all have clock "controllers" I'd assume you meant "this crypto ip does not take a clock input on some SoCs", correct ? If that is what you mean, giving the list of the SoCs which - according to you - do or don't take a clock ip input would be helpful. > > Signed-off-by: Alexey Romanov <avromanov@salutedevices.com> > --- > drivers/crypto/amlogic/amlogic-gxl-core.c | 11 ++--------- > 1 file changed, 2 insertions(+), 9 deletions(-) > > diff --git a/drivers/crypto/amlogic/amlogic-gxl-core.c b/drivers/crypto/amlogic/amlogic-gxl-core.c > index 35ec64df5b3a..a58644be76e9 100644 > --- a/drivers/crypto/amlogic/amlogic-gxl-core.c > +++ b/drivers/crypto/amlogic/amlogic-gxl-core.c > @@ -263,16 +263,10 @@ static int meson_crypto_probe(struct platform_device *pdev) > dev_err(&pdev->dev, "Cannot request MMIO err=%d\n", err); > return err; > } > - mc->busclk = devm_clk_get(&pdev->dev, "blkmv"); > + mc->busclk = devm_clk_get_optional_enabled(&pdev->dev, "blkmv"); Assuming some SoC actually don't have an input clock (I'm not convinced), the clock still ain't optional for the ones which do. Use the compatible to properly claim the ressource (or not) > if (IS_ERR(mc->busclk)) { > err = PTR_ERR(mc->busclk); > - dev_err(&pdev->dev, "Cannot get core clock err=%d\n", err); > - return err; > - } > - > - err = clk_prepare_enable(mc->busclk); > - if (err != 0) { > - dev_err(&pdev->dev, "Cannot prepare_enable busclk\n"); > + dev_err(&pdev->dev, "Cannot get and enable core clock err=%d\n", err); > return err; > } > > @@ -300,7 +294,6 @@ static int meson_crypto_probe(struct platform_device *pdev) > meson_unregister_algs(mc); > error_flow: > meson_free_chanlist(mc, mc->flow_cnt - 1); > - clk_disable_unprepare(mc->busclk); > return err; > }
diff --git a/drivers/crypto/amlogic/amlogic-gxl-core.c b/drivers/crypto/amlogic/amlogic-gxl-core.c index 35ec64df5b3a..a58644be76e9 100644 --- a/drivers/crypto/amlogic/amlogic-gxl-core.c +++ b/drivers/crypto/amlogic/amlogic-gxl-core.c @@ -263,16 +263,10 @@ static int meson_crypto_probe(struct platform_device *pdev) dev_err(&pdev->dev, "Cannot request MMIO err=%d\n", err); return err; } - mc->busclk = devm_clk_get(&pdev->dev, "blkmv"); + mc->busclk = devm_clk_get_optional_enabled(&pdev->dev, "blkmv"); if (IS_ERR(mc->busclk)) { err = PTR_ERR(mc->busclk); - dev_err(&pdev->dev, "Cannot get core clock err=%d\n", err); - return err; - } - - err = clk_prepare_enable(mc->busclk); - if (err != 0) { - dev_err(&pdev->dev, "Cannot prepare_enable busclk\n"); + dev_err(&pdev->dev, "Cannot get and enable core clock err=%d\n", err); return err; } @@ -300,7 +294,6 @@ static int meson_crypto_probe(struct platform_device *pdev) meson_unregister_algs(mc); error_flow: meson_free_chanlist(mc, mc->flow_cnt - 1); - clk_disable_unprepare(mc->busclk); return err; }
Not all Amlogic SoC's uses CLK controller. Signed-off-by: Alexey Romanov <avromanov@salutedevices.com> --- drivers/crypto/amlogic/amlogic-gxl-core.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-)