[v1,2/4] clk: meson: a1: pll: determine maximum register in regmap config

Commit Message

Dmitry Rokosov March 20, 2024, 3:54 p.m. UTC

When the max_register value is not set, the regmap debugfs 'registers'
file does not display the entire range of the regmap.

Signed-off-by: Dmitry Rokosov <[e-mail]>
---
 drivers/clk/meson/a1-pll.c | 1 +
 1 file changed, 1 insertion(+)

Patch

diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c
index 00e06d03445b..60b2e53e7e51 100644
--- a/drivers/clk/meson/a1-pll.c
+++ b/drivers/clk/meson/a1-pll.c
@@ -299,6 +299,7 @@  static struct regmap_config a1_pll_regmap_cfg = {
 	.reg_bits   = 32,
 	.val_bits   = 32,
 	.reg_stride = 4,
+	.max_register = ANACTRL_HIFIPLL_STS,
 };
 
 static struct meson_clk_hw_data a1_pll_clks = {