| Message ID | 20240325235311.411920-1-jan.dakinevich@salutedevices.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [RFC,v2] ASoC: meson: g12a-toacodec: rework the definition of bits | expand |
On Tue 26 Mar 2024 at 02:53, Jan Dakinevich <jan.dakinevich@salutedevices.com> wrote: > There is a lot of defines, but almost all of them are not used. Lets > rework them: Thanks for noticing. Please start by removing what's unused. > > - keep separate the definition for different platforms to make easier > checking that they match documentation. > > - use LSB/MSB sufixes for uniformity. I'd be in favor of dropping these suffixes completely. > > - don't use hard-coded values for already declared defines. > > Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com> > --- > Links: > > [1] https://lore.kernel.org/lkml/20240314232201.2102178-1-jan.dakinevich@salutedevices.com/ > > Changes v1 -> v2: > - Detached from v1's series (patch 7). > - Fixed my wrong understanding of SOC_SINGLE's input parameters. > > sound/soc/meson/g12a-toacodec.c | 79 ++++++++++++++++++++------------- > 1 file changed, 49 insertions(+), 30 deletions(-) > > diff --git a/sound/soc/meson/g12a-toacodec.c b/sound/soc/meson/g12a-toacodec.c > index 531bb8707a3e..22181f4bab72 100644 > --- a/sound/soc/meson/g12a-toacodec.c > +++ b/sound/soc/meson/g12a-toacodec.c > @@ -20,26 +20,37 @@ > #define G12A_TOACODEC_DRV_NAME "g12a-toacodec" > > #define TOACODEC_CTRL0 0x0 > -#define CTRL0_ENABLE_SHIFT 31 > -#define CTRL0_DAT_SEL_SM1_MSB 19 > -#define CTRL0_DAT_SEL_SM1_LSB 18 > -#define CTRL0_DAT_SEL_MSB 15 > -#define CTRL0_DAT_SEL_LSB 14 > -#define CTRL0_LANE_SEL_SM1 16 > -#define CTRL0_LANE_SEL 12 > -#define CTRL0_LRCLK_SEL_SM1_MSB 14 > -#define CTRL0_LRCLK_SEL_SM1_LSB 12 > -#define CTRL0_LRCLK_SEL_MSB 9 > -#define CTRL0_LRCLK_SEL_LSB 8 > -#define CTRL0_LRCLK_INV_SM1 BIT(10) > -#define CTRL0_BLK_CAP_INV_SM1 BIT(9) > -#define CTRL0_BLK_CAP_INV BIT(7) > -#define CTRL0_BCLK_O_INV_SM1 BIT(8) > -#define CTRL0_BCLK_O_INV BIT(6) > -#define CTRL0_BCLK_SEL_SM1_MSB 6 > -#define CTRL0_BCLK_SEL_MSB 5 > -#define CTRL0_BCLK_SEL_LSB 4 > -#define CTRL0_MCLK_SEL GENMASK(2, 0) > + > +/* Common bits */ > +#define CTRL0_ENABLE_SHIFT 31 > +#define CTRL0_MCLK_SEL GENMASK(2, 0) > + > +/* G12A bits */ > +#define CTRL0_DAT_SEL_G12A_MSB 15 > +#define CTRL0_DAT_SEL_G12A_LSB 14 > +#define CTRL0_LANE_SEL_G12A_MSB 13 > +#define CTRL0_LANE_SEL_G12A_LSB 12 > +#define CTRL0_LANE_SEL_G12A_MAX 3 > +#define CTRL0_LRCLK_SEL_G12A_MSB 9 > +#define CTRL0_LRCLK_SEL_G12A_LSB 8 > +#define CTRL0_BLK_CAP_INV_G12A BIT(7) > +#define CTRL0_BCLK_O_INV_G12A BIT(6) > +#define CTRL0_BCLK_SEL_G12A_MSB 5 > +#define CTRL0_BCLK_SEL_G12A_LSB 4 > + > +/* SM1 bits */ > +#define CTRL0_DAT_SEL_SM1_MSB 19 > +#define CTRL0_DAT_SEL_SM1_LSB 18 > +#define CTRL0_LANE_SEL_SM1_MSB 17 > +#define CTRL0_LANE_SEL_SM1_LSB 16 > +#define CTRL0_LANE_SEL_SM1_MAX 3 > +#define CTRL0_LRCLK_SEL_SM1_MSB 14 > +#define CTRL0_LRCLK_SEL_SM1_LSB 12 > +#define CTRL0_LRCLK_INV_SM1 BIT(10) > +#define CTRL0_BLK_CAP_INV_SM1 BIT(9) > +#define CTRL0_BCLK_O_INV_SM1 BIT(8) > +#define CTRL0_BCLK_SEL_SM1_MSB 6 > +#define CTRL0_BCLK_SEL_SM1_LSB 4 > > #define TOACODEC_OUT_CHMAX 2 > > @@ -108,7 +119,7 @@ static int g12a_toacodec_mux_put_enum(struct snd_kcontrol *kcontrol, > } > > static SOC_ENUM_SINGLE_DECL(g12a_toacodec_mux_enum, TOACODEC_CTRL0, > - CTRL0_DAT_SEL_LSB, > + CTRL0_DAT_SEL_G12A_LSB, > g12a_toacodec_mux_texts); > > static SOC_ENUM_SINGLE_DECL(sm1_toacodec_mux_enum, TOACODEC_CTRL0, > @@ -210,7 +221,7 @@ static int g12a_toacodec_component_probe(struct snd_soc_component *c) > { > /* Initialize the static clock parameters */ > return snd_soc_component_write(c, TOACODEC_CTRL0, > - CTRL0_BLK_CAP_INV); > + CTRL0_BLK_CAP_INV_G12A); > } > > static int sm1_toacodec_component_probe(struct snd_soc_component *c) > @@ -229,11 +240,13 @@ static const struct snd_soc_dapm_route g12a_toacodec_routes[] = { > }; > > static const struct snd_kcontrol_new g12a_toacodec_controls[] = { > - SOC_SINGLE("Lane Select", TOACODEC_CTRL0, CTRL0_LANE_SEL, 3, 0), > + SOC_SINGLE("Lane Select", TOACODEC_CTRL0, CTRL0_LANE_SEL_G12A_LSB, > + CTRL0_LANE_SEL_G12A_MAX, 0), > }; > > static const struct snd_kcontrol_new sm1_toacodec_controls[] = { > - SOC_SINGLE("Lane Select", TOACODEC_CTRL0, CTRL0_LANE_SEL_SM1, 3, 0), > + SOC_SINGLE("Lane Select", TOACODEC_CTRL0, CTRL0_LANE_SEL_SM1_LSB, > + CTRL0_LANE_SEL_SM1_MAX, 0), > }; > > static const struct snd_soc_component_driver g12a_toacodec_component_drv = { > @@ -266,16 +279,22 @@ static const struct regmap_config g12a_toacodec_regmap_cfg = { > > static const struct g12a_toacodec_match_data g12a_toacodec_match_data = { > .component_drv = &g12a_toacodec_component_drv, > - .field_dat_sel = REG_FIELD(TOACODEC_CTRL0, 14, 15), > - .field_lrclk_sel = REG_FIELD(TOACODEC_CTRL0, 8, 9), > - .field_bclk_sel = REG_FIELD(TOACODEC_CTRL0, 4, 5), > + .field_dat_sel = REG_FIELD(TOACODEC_CTRL0, CTRL0_DAT_SEL_G12A_LSB, > + CTRL0_DAT_SEL_G12A_MSB), > + .field_lrclk_sel = REG_FIELD(TOACODEC_CTRL0, CTRL0_LRCLK_SEL_G12A_LSB, > + CTRL0_LRCLK_SEL_G12A_MSB), > + .field_bclk_sel = REG_FIELD(TOACODEC_CTRL0, CTRL0_BCLK_SEL_G12A_LSB, > + CTRL0_BCLK_SEL_G12A_MSB), > }; > > static const struct g12a_toacodec_match_data sm1_toacodec_match_data = { > .component_drv = &sm1_toacodec_component_drv, > - .field_dat_sel = REG_FIELD(TOACODEC_CTRL0, 18, 19), > - .field_lrclk_sel = REG_FIELD(TOACODEC_CTRL0, 12, 14), > - .field_bclk_sel = REG_FIELD(TOACODEC_CTRL0, 4, 6), > + .field_dat_sel = REG_FIELD(TOACODEC_CTRL0, CTRL0_DAT_SEL_SM1_LSB, > + CTRL0_DAT_SEL_SM1_MSB), > + .field_lrclk_sel = REG_FIELD(TOACODEC_CTRL0, CTRL0_LRCLK_SEL_SM1_LSB, > + CTRL0_LRCLK_SEL_SM1_MSB), > + .field_bclk_sel = REG_FIELD(TOACODEC_CTRL0, CTRL0_BCLK_SEL_SM1_LSB, > + CTRL0_BCLK_SEL_SM1_MSB), Those defines are already platform specific by the structure holding them and the defines you have added are not helping readability. I don't see the point to see. I'd prefer to keep the field defined as they are. > }; > > static const struct of_device_id g12a_toacodec_of_match[] = {
On 3/26/24 18:15, Jerome Brunet wrote: > > On Tue 26 Mar 2024 at 02:53, Jan Dakinevich <jan.dakinevich@salutedevices.com> wrote: > >> There is a lot of defines, but almost all of them are not used. Lets >> rework them: > > Thanks for noticing. Please start by removing what's unused. > I mean, that some values are named. But then numbers are used instead names. >> >> - keep separate the definition for different platforms to make easier >> checking that they match documentation. >> >> - use LSB/MSB sufixes for uniformity. > > I'd be in favor of dropping these suffixes completely. > >> >> - don't use hard-coded values for already declared defines. >> >> Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com> >> --- >> Links: >> >> [1] https://lore.kernel.org/lkml/20240314232201.2102178-1-jan.dakinevich@salutedevices.com/ >> >> Changes v1 -> v2: >> - Detached from v1's series (patch 7). >> - Fixed my wrong understanding of SOC_SINGLE's input parameters. >> >> sound/soc/meson/g12a-toacodec.c | 79 ++++++++++++++++++++------------- >> 1 file changed, 49 insertions(+), 30 deletions(-) >> >> diff --git a/sound/soc/meson/g12a-toacodec.c b/sound/soc/meson/g12a-toacodec.c >> index 531bb8707a3e..22181f4bab72 100644 >> --- a/sound/soc/meson/g12a-toacodec.c >> +++ b/sound/soc/meson/g12a-toacodec.c >> @@ -20,26 +20,37 @@ >> #define G12A_TOACODEC_DRV_NAME "g12a-toacodec" >> >> #define TOACODEC_CTRL0 0x0 >> -#define CTRL0_ENABLE_SHIFT 31 >> -#define CTRL0_DAT_SEL_SM1_MSB 19 >> -#define CTRL0_DAT_SEL_SM1_LSB 18 >> -#define CTRL0_DAT_SEL_MSB 15 >> -#define CTRL0_DAT_SEL_LSB 14 >> -#define CTRL0_LANE_SEL_SM1 16 >> -#define CTRL0_LANE_SEL 12 >> -#define CTRL0_LRCLK_SEL_SM1_MSB 14 >> -#define CTRL0_LRCLK_SEL_SM1_LSB 12 >> -#define CTRL0_LRCLK_SEL_MSB 9 >> -#define CTRL0_LRCLK_SEL_LSB 8 >> -#define CTRL0_LRCLK_INV_SM1 BIT(10) >> -#define CTRL0_BLK_CAP_INV_SM1 BIT(9) >> -#define CTRL0_BLK_CAP_INV BIT(7) >> -#define CTRL0_BCLK_O_INV_SM1 BIT(8) >> -#define CTRL0_BCLK_O_INV BIT(6) >> -#define CTRL0_BCLK_SEL_SM1_MSB 6 >> -#define CTRL0_BCLK_SEL_MSB 5 >> -#define CTRL0_BCLK_SEL_LSB 4 >> -#define CTRL0_MCLK_SEL GENMASK(2, 0) >> + >> +/* Common bits */ >> +#define CTRL0_ENABLE_SHIFT 31 >> +#define CTRL0_MCLK_SEL GENMASK(2, 0) >> + >> +/* G12A bits */ >> +#define CTRL0_DAT_SEL_G12A_MSB 15 >> +#define CTRL0_DAT_SEL_G12A_LSB 14 >> +#define CTRL0_LANE_SEL_G12A_MSB 13 >> +#define CTRL0_LANE_SEL_G12A_LSB 12 >> +#define CTRL0_LANE_SEL_G12A_MAX 3 >> +#define CTRL0_LRCLK_SEL_G12A_MSB 9 >> +#define CTRL0_LRCLK_SEL_G12A_LSB 8 >> +#define CTRL0_BLK_CAP_INV_G12A BIT(7) >> +#define CTRL0_BCLK_O_INV_G12A BIT(6) >> +#define CTRL0_BCLK_SEL_G12A_MSB 5 >> +#define CTRL0_BCLK_SEL_G12A_LSB 4 >> + >> +/* SM1 bits */ >> +#define CTRL0_DAT_SEL_SM1_MSB 19 >> +#define CTRL0_DAT_SEL_SM1_LSB 18 >> +#define CTRL0_LANE_SEL_SM1_MSB 17 >> +#define CTRL0_LANE_SEL_SM1_LSB 16 >> +#define CTRL0_LANE_SEL_SM1_MAX 3 >> +#define CTRL0_LRCLK_SEL_SM1_MSB 14 >> +#define CTRL0_LRCLK_SEL_SM1_LSB 12 >> +#define CTRL0_LRCLK_INV_SM1 BIT(10) >> +#define CTRL0_BLK_CAP_INV_SM1 BIT(9) >> +#define CTRL0_BCLK_O_INV_SM1 BIT(8) >> +#define CTRL0_BCLK_SEL_SM1_MSB 6 >> +#define CTRL0_BCLK_SEL_SM1_LSB 4 >> >> #define TOACODEC_OUT_CHMAX 2 >> >> @@ -108,7 +119,7 @@ static int g12a_toacodec_mux_put_enum(struct snd_kcontrol *kcontrol, >> } >> >> static SOC_ENUM_SINGLE_DECL(g12a_toacodec_mux_enum, TOACODEC_CTRL0, >> - CTRL0_DAT_SEL_LSB, >> + CTRL0_DAT_SEL_G12A_LSB, >> g12a_toacodec_mux_texts); >> >> static SOC_ENUM_SINGLE_DECL(sm1_toacodec_mux_enum, TOACODEC_CTRL0, >> @@ -210,7 +221,7 @@ static int g12a_toacodec_component_probe(struct snd_soc_component *c) >> { >> /* Initialize the static clock parameters */ >> return snd_soc_component_write(c, TOACODEC_CTRL0, >> - CTRL0_BLK_CAP_INV); >> + CTRL0_BLK_CAP_INV_G12A); >> } >> >> static int sm1_toacodec_component_probe(struct snd_soc_component *c) >> @@ -229,11 +240,13 @@ static const struct snd_soc_dapm_route g12a_toacodec_routes[] = { >> }; >> >> static const struct snd_kcontrol_new g12a_toacodec_controls[] = { >> - SOC_SINGLE("Lane Select", TOACODEC_CTRL0, CTRL0_LANE_SEL, 3, 0), >> + SOC_SINGLE("Lane Select", TOACODEC_CTRL0, CTRL0_LANE_SEL_G12A_LSB, >> + CTRL0_LANE_SEL_G12A_MAX, 0), >> }; >> >> static const struct snd_kcontrol_new sm1_toacodec_controls[] = { >> - SOC_SINGLE("Lane Select", TOACODEC_CTRL0, CTRL0_LANE_SEL_SM1, 3, 0), >> + SOC_SINGLE("Lane Select", TOACODEC_CTRL0, CTRL0_LANE_SEL_SM1_LSB, >> + CTRL0_LANE_SEL_SM1_MAX, 0), >> }; >> >> static const struct snd_soc_component_driver g12a_toacodec_component_drv = { >> @@ -266,16 +279,22 @@ static const struct regmap_config g12a_toacodec_regmap_cfg = { >> >> static const struct g12a_toacodec_match_data g12a_toacodec_match_data = { >> .component_drv = &g12a_toacodec_component_drv, >> - .field_dat_sel = REG_FIELD(TOACODEC_CTRL0, 14, 15), >> - .field_lrclk_sel = REG_FIELD(TOACODEC_CTRL0, 8, 9), >> - .field_bclk_sel = REG_FIELD(TOACODEC_CTRL0, 4, 5), >> + .field_dat_sel = REG_FIELD(TOACODEC_CTRL0, CTRL0_DAT_SEL_G12A_LSB, >> + CTRL0_DAT_SEL_G12A_MSB), >> + .field_lrclk_sel = REG_FIELD(TOACODEC_CTRL0, CTRL0_LRCLK_SEL_G12A_LSB, >> + CTRL0_LRCLK_SEL_G12A_MSB), >> + .field_bclk_sel = REG_FIELD(TOACODEC_CTRL0, CTRL0_BCLK_SEL_G12A_LSB, >> + CTRL0_BCLK_SEL_G12A_MSB), >> }; >> >> static const struct g12a_toacodec_match_data sm1_toacodec_match_data = { >> .component_drv = &sm1_toacodec_component_drv, >> - .field_dat_sel = REG_FIELD(TOACODEC_CTRL0, 18, 19), >> - .field_lrclk_sel = REG_FIELD(TOACODEC_CTRL0, 12, 14), >> - .field_bclk_sel = REG_FIELD(TOACODEC_CTRL0, 4, 6), >> + .field_dat_sel = REG_FIELD(TOACODEC_CTRL0, CTRL0_DAT_SEL_SM1_LSB, >> + CTRL0_DAT_SEL_SM1_MSB), >> + .field_lrclk_sel = REG_FIELD(TOACODEC_CTRL0, CTRL0_LRCLK_SEL_SM1_LSB, >> + CTRL0_LRCLK_SEL_SM1_MSB), >> + .field_bclk_sel = REG_FIELD(TOACODEC_CTRL0, CTRL0_BCLK_SEL_SM1_LSB, >> + CTRL0_BCLK_SEL_SM1_MSB), > > Those defines are already platform specific by the structure holding > them and the defines you have added are not helping readability. > These values are duplicated. Would it be reasonable to remove them from defines? > I don't see the point to see. > I'd prefer to keep the field defined as they are. > Main goal of this patch is to rearrange definitions by platforms. From my point it is quite difficult to read things like this: #define CTRL0_LANE_SEL_SM1 16 #define CTRL0_LANE_SEL 12 #define CTRL0_LRCLK_SEL_SM1_MSB 14 #define CTRL0_LRCLK_SEL_SM1_LSB 12 #define CTRL0_LRCLK_SEL_MSB 9 #define CTRL0_LRCLK_SEL_LSB 8 I am going to add one more platforms, and this will get worse. >> }; >> >> static const struct of_device_id g12a_toacodec_of_match[] = { > >
diff --git a/sound/soc/meson/g12a-toacodec.c b/sound/soc/meson/g12a-toacodec.c index 531bb8707a3e..22181f4bab72 100644 --- a/sound/soc/meson/g12a-toacodec.c +++ b/sound/soc/meson/g12a-toacodec.c @@ -20,26 +20,37 @@ #define G12A_TOACODEC_DRV_NAME "g12a-toacodec" #define TOACODEC_CTRL0 0x0 -#define CTRL0_ENABLE_SHIFT 31 -#define CTRL0_DAT_SEL_SM1_MSB 19 -#define CTRL0_DAT_SEL_SM1_LSB 18 -#define CTRL0_DAT_SEL_MSB 15 -#define CTRL0_DAT_SEL_LSB 14 -#define CTRL0_LANE_SEL_SM1 16 -#define CTRL0_LANE_SEL 12 -#define CTRL0_LRCLK_SEL_SM1_MSB 14 -#define CTRL0_LRCLK_SEL_SM1_LSB 12 -#define CTRL0_LRCLK_SEL_MSB 9 -#define CTRL0_LRCLK_SEL_LSB 8 -#define CTRL0_LRCLK_INV_SM1 BIT(10) -#define CTRL0_BLK_CAP_INV_SM1 BIT(9) -#define CTRL0_BLK_CAP_INV BIT(7) -#define CTRL0_BCLK_O_INV_SM1 BIT(8) -#define CTRL0_BCLK_O_INV BIT(6) -#define CTRL0_BCLK_SEL_SM1_MSB 6 -#define CTRL0_BCLK_SEL_MSB 5 -#define CTRL0_BCLK_SEL_LSB 4 -#define CTRL0_MCLK_SEL GENMASK(2, 0) + +/* Common bits */ +#define CTRL0_ENABLE_SHIFT 31 +#define CTRL0_MCLK_SEL GENMASK(2, 0) + +/* G12A bits */ +#define CTRL0_DAT_SEL_G12A_MSB 15 +#define CTRL0_DAT_SEL_G12A_LSB 14 +#define CTRL0_LANE_SEL_G12A_MSB 13 +#define CTRL0_LANE_SEL_G12A_LSB 12 +#define CTRL0_LANE_SEL_G12A_MAX 3 +#define CTRL0_LRCLK_SEL_G12A_MSB 9 +#define CTRL0_LRCLK_SEL_G12A_LSB 8 +#define CTRL0_BLK_CAP_INV_G12A BIT(7) +#define CTRL0_BCLK_O_INV_G12A BIT(6) +#define CTRL0_BCLK_SEL_G12A_MSB 5 +#define CTRL0_BCLK_SEL_G12A_LSB 4 + +/* SM1 bits */ +#define CTRL0_DAT_SEL_SM1_MSB 19 +#define CTRL0_DAT_SEL_SM1_LSB 18 +#define CTRL0_LANE_SEL_SM1_MSB 17 +#define CTRL0_LANE_SEL_SM1_LSB 16 +#define CTRL0_LANE_SEL_SM1_MAX 3 +#define CTRL0_LRCLK_SEL_SM1_MSB 14 +#define CTRL0_LRCLK_SEL_SM1_LSB 12 +#define CTRL0_LRCLK_INV_SM1 BIT(10) +#define CTRL0_BLK_CAP_INV_SM1 BIT(9) +#define CTRL0_BCLK_O_INV_SM1 BIT(8) +#define CTRL0_BCLK_SEL_SM1_MSB 6 +#define CTRL0_BCLK_SEL_SM1_LSB 4 #define TOACODEC_OUT_CHMAX 2 @@ -108,7 +119,7 @@ static int g12a_toacodec_mux_put_enum(struct snd_kcontrol *kcontrol, } static SOC_ENUM_SINGLE_DECL(g12a_toacodec_mux_enum, TOACODEC_CTRL0, - CTRL0_DAT_SEL_LSB, + CTRL0_DAT_SEL_G12A_LSB, g12a_toacodec_mux_texts); static SOC_ENUM_SINGLE_DECL(sm1_toacodec_mux_enum, TOACODEC_CTRL0, @@ -210,7 +221,7 @@ static int g12a_toacodec_component_probe(struct snd_soc_component *c) { /* Initialize the static clock parameters */ return snd_soc_component_write(c, TOACODEC_CTRL0, - CTRL0_BLK_CAP_INV); + CTRL0_BLK_CAP_INV_G12A); } static int sm1_toacodec_component_probe(struct snd_soc_component *c) @@ -229,11 +240,13 @@ static const struct snd_soc_dapm_route g12a_toacodec_routes[] = { }; static const struct snd_kcontrol_new g12a_toacodec_controls[] = { - SOC_SINGLE("Lane Select", TOACODEC_CTRL0, CTRL0_LANE_SEL, 3, 0), + SOC_SINGLE("Lane Select", TOACODEC_CTRL0, CTRL0_LANE_SEL_G12A_LSB, + CTRL0_LANE_SEL_G12A_MAX, 0), }; static const struct snd_kcontrol_new sm1_toacodec_controls[] = { - SOC_SINGLE("Lane Select", TOACODEC_CTRL0, CTRL0_LANE_SEL_SM1, 3, 0), + SOC_SINGLE("Lane Select", TOACODEC_CTRL0, CTRL0_LANE_SEL_SM1_LSB, + CTRL0_LANE_SEL_SM1_MAX, 0), }; static const struct snd_soc_component_driver g12a_toacodec_component_drv = { @@ -266,16 +279,22 @@ static const struct regmap_config g12a_toacodec_regmap_cfg = { static const struct g12a_toacodec_match_data g12a_toacodec_match_data = { .component_drv = &g12a_toacodec_component_drv, - .field_dat_sel = REG_FIELD(TOACODEC_CTRL0, 14, 15), - .field_lrclk_sel = REG_FIELD(TOACODEC_CTRL0, 8, 9), - .field_bclk_sel = REG_FIELD(TOACODEC_CTRL0, 4, 5), + .field_dat_sel = REG_FIELD(TOACODEC_CTRL0, CTRL0_DAT_SEL_G12A_LSB, + CTRL0_DAT_SEL_G12A_MSB), + .field_lrclk_sel = REG_FIELD(TOACODEC_CTRL0, CTRL0_LRCLK_SEL_G12A_LSB, + CTRL0_LRCLK_SEL_G12A_MSB), + .field_bclk_sel = REG_FIELD(TOACODEC_CTRL0, CTRL0_BCLK_SEL_G12A_LSB, + CTRL0_BCLK_SEL_G12A_MSB), }; static const struct g12a_toacodec_match_data sm1_toacodec_match_data = { .component_drv = &sm1_toacodec_component_drv, - .field_dat_sel = REG_FIELD(TOACODEC_CTRL0, 18, 19), - .field_lrclk_sel = REG_FIELD(TOACODEC_CTRL0, 12, 14), - .field_bclk_sel = REG_FIELD(TOACODEC_CTRL0, 4, 6), + .field_dat_sel = REG_FIELD(TOACODEC_CTRL0, CTRL0_DAT_SEL_SM1_LSB, + CTRL0_DAT_SEL_SM1_MSB), + .field_lrclk_sel = REG_FIELD(TOACODEC_CTRL0, CTRL0_LRCLK_SEL_SM1_LSB, + CTRL0_LRCLK_SEL_SM1_MSB), + .field_bclk_sel = REG_FIELD(TOACODEC_CTRL0, CTRL0_BCLK_SEL_SM1_LSB, + CTRL0_BCLK_SEL_SM1_MSB), }; static const struct of_device_id g12a_toacodec_of_match[] = {
There is a lot of defines, but almost all of them are not used. Lets rework them: - keep separate the definition for different platforms to make easier checking that they match documentation. - use LSB/MSB sufixes for uniformity. - don't use hard-coded values for already declared defines. Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com> --- Links: [1] https://lore.kernel.org/lkml/20240314232201.2102178-1-jan.dakinevich@salutedevices.com/ Changes v1 -> v2: - Detached from v1's series (patch 7). - Fixed my wrong understanding of SOC_SINGLE's input parameters. sound/soc/meson/g12a-toacodec.c | 79 ++++++++++++++++++++------------- 1 file changed, 49 insertions(+), 30 deletions(-)