From patchwork Mon Jun 17 13:50:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Trevor Gamblin X-Patchwork-Id: 13700887 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 09653C2BA15 for ; Mon, 17 Jun 2024 15:01:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=osgwKwCWpXNbY8NIYMIShx0Skwk7Qe4IJ5ZWVPz8Qog=; b=egajteAlL8Q3iX 7d4EdVVNdYWQnsU4s5hojQjUV/M2W4m3zjdAVNFwPmTmP6OSgVaJrglk+Ij9kapxvhXzU0RntsD4c EUHe6NbwCbQFV+4CAF9XErfBWrOXE5kMyEa3q1GNzMkDxNHjBkrK9Zeb7OFR+TA+RWHxnNrWUTuGV /wDZFPMA3zVj95m9XkeHz0eO1QNJwKfyysUYDiGgyetlLBWNkK/6VlJi4eOje3MxPFKOQhzOzh5ul C0kUKCEki8WibutrPtYyBETd4F+nLefXkojm6p5bw9no8xYj+dRMO7oJCin1rjyHUs3QJd/karkk2 yzJEPqTO4qBhbaNYdgnQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sJDri-0000000BKoC-0k27; Mon, 17 Jun 2024 15:01:50 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sJClV-0000000Ay1M-2ast for linux-amlogic@bombadil.infradead.org; Mon, 17 Jun 2024 13:51:22 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Cc:To:In-Reply-To:References: Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Sender:Reply-To:Content-ID:Content-Description; bh=AKnuVsDBtdHGm81QL99oZtdVbIW3JEVTOu6hlNZPjXg=; b=H4JKiuf+/H2K2pDW7QUh8s/lry 1A2r/xlklaU2Wyjs+Ro+g0ZJ9T0MRGcRzKS348Un9e8wCxNhX42YRkU1MivwIWIA0qboEWDz6589e W+vGinfM/qbbVVkRsvj05KcP4lBRyh6RjlU3VF6MeI7ylvriYgI7DtPpQKUUoHWOkxA08ULAoVA6j 4kuvSS0CdQjHlJwDq8DrB8PoPEhTiln5Xmt0oEXkFW8nFqdRkdNJBEZyqE6j7w+VhWXMFOGe2Mo6H dwzx1z7xIrMEe9B2LBYsEP82yeVV8hbPDQ6AYm8Iy8Vgeh25RftSmlcnGp/jwcoyn1q9Lsh8LUYUe Ih5TT0OQ==; Received: from mail-vk1-xa33.google.com ([2607:f8b0:4864:20::a33]) by desiato.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sJClS-00000006RE8-0Tyd for linux-amlogic@lists.infradead.org; Mon, 17 Jun 2024 13:51:20 +0000 Received: by mail-vk1-xa33.google.com with SMTP id 71dfb90a1353d-4e4f0020ca3so1319448e0c.2 for ; Mon, 17 Jun 2024 06:51:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1718632273; x=1719237073; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=AKnuVsDBtdHGm81QL99oZtdVbIW3JEVTOu6hlNZPjXg=; b=hvoHpOc6QZ+3tKUNT6L7zmg0si9jzTodZx/J7P/Cnf4N+u39FT8HbpUc4ysi5gkJZN 6vZqOfISn6P7YhLdjOGiDCuJuZzYEgBAy+ntiwUVtpcjnDDRB0ZaeaaN7CBTfCBo7a4F vexW/xDL0tk8+5FmTVtQr+Y45612FiDD3Z9qc0MrJ2R/mgjmuBN7SKW9rsTzLwH09pzd FfC6QZ2V1cWxcTXWOo+GwEUJCe4A/3yH3tRUfmnnCkGt7HOCjPKuxj5mQs3CT4nYCb/w LpPmXRWXFONhvZANXLRU//xRkleFwLrDVYpUdfI35ri5xB6fBhPx9YFR7sYpf1lJP1cp Q30g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718632273; x=1719237073; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AKnuVsDBtdHGm81QL99oZtdVbIW3JEVTOu6hlNZPjXg=; b=OL9G8ZmxGH0d6yS9AX8i3Uz3epduldZnUq832FlfPPZx6jGYhcpTZ6lQIA5G8lIqBa V7M5D79kPqy07BGofRO0XPLbhEtrzSxzxyqVi3yPEqNVV3XjFHteinSptdyIZfJKXP4d VyPPjBILoiTexpnatKpRaDuOQWovXL2og1jRPdrZuCfZjlRRY3vDZLavKtXQcxulIDwl ZAXukT7ua2r5M5Tag5tVRK0QDK+w0+qz6HiPx4mGRboiLRjKHmgXjROpbasoS1gWVzQ1 tXJizp1f6qF9/d+du8aDIqZ25i+TScaA0HNWB5Fp8ouNlpNT7jEtF9WBWGoUa7DmCAyA 7TzQ== X-Forwarded-Encrypted: i=1; AJvYcCUb0PK4g7RRdgASOlJ7qutMrufy8+oshMn1ZJ9XShs6ApTCAgsN6CcvPFSPZ6P+KO3ikCw/ycYATaat7hLJAM8fTwVFDFeh28IPeEaW1tZjcAw= X-Gm-Message-State: AOJu0YxFnxdvrqhnW/kXuzw5nu3HhktlWRd1+2pBWPyNU35zNQ/GRmxK jOh9dfnbSe3GzOSei2mJtZoQd3IHDvkAs7V7EQwi7qMCYy4HnK5jORfTBBufM7s= X-Google-Smtp-Source: AGHT+IHFy1tuFMwxa7P6sFsjYvAHUS1dIKxzAj2HLRYOAmnW2Gug4qjgVMG/WpGom5Qua5PdHz8vPQ== X-Received: by 2002:a05:6122:915:b0:4ec:efca:d2b with SMTP id 71dfb90a1353d-4ee3e59c40amr7925275e0c.8.1718632272678; Mon, 17 Jun 2024 06:51:12 -0700 (PDT) Received: from megalith.oryx-coho.ts.net (d24-150-219-207.home.cgocable.net. [24.150.219.207]) by smtp.gmail.com with ESMTPSA id af79cd13be357-798aaecc004sm432892285a.31.2024.06.17.06.51.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jun 2024 06:51:12 -0700 (PDT) From: Trevor Gamblin Date: Mon, 17 Jun 2024 09:50:21 -0400 Subject: [PATCH v3 41/41] iio: trigger: stm32-timer-trigger: make use of regmap_clear_bits(), regmap_set_bits() MIME-Version: 1.0 Message-Id: <20240617-review-v3-41-88d1338c4cca@baylibre.com> References: <20240617-review-v3-0-88d1338c4cca@baylibre.com> In-Reply-To: <20240617-review-v3-0-88d1338c4cca@baylibre.com> To: Jonathan Cameron , Lars-Peter Clausen , Dmitry Rokosov , Michael Hennerich , Cosmin Tanislav , Chen-Yu Tsai , Hans de Goede , Ray Jui , Scott Branden , Broadcom internal kernel review list , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Saravanan Sekar , Orson Zhai , Baolin Wang , Chunyan Zhang , Maxime Coquelin , Alexandre Torgue , =?utf-8?q?Nuno_S=C3=A1?= , Linus Walleij , Jean-Baptiste Maneyrol , Crt Mori Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Trevor Gamblin X-Mailer: b4 0.13.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240617_145118_500834_6801E6BD X-CRM114-Status: GOOD ( 12.89 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org Instead of using regmap_update_bits() and passing the mask twice, use regmap_set_bits(). Instead of using regmap_update_bits() and passing val = 0, use regmap_clear_bits(). Suggested-by: Uwe Kleine-König Signed-off-by: Trevor Gamblin --- drivers/iio/trigger/stm32-timer-trigger.c | 34 +++++++++++++++---------------- 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/drivers/iio/trigger/stm32-timer-trigger.c b/drivers/iio/trigger/stm32-timer-trigger.c index d76444030a28..0684329956d9 100644 --- a/drivers/iio/trigger/stm32-timer-trigger.c +++ b/drivers/iio/trigger/stm32-timer-trigger.c @@ -158,7 +158,7 @@ static int stm32_timer_start(struct stm32_timer_trigger *priv, regmap_write(priv->regmap, TIM_PSC, prescaler); regmap_write(priv->regmap, TIM_ARR, prd - 1); - regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE); + regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE); /* Force master mode to update mode */ if (stm32_timer_is_trgo2_name(trig->name)) @@ -169,10 +169,10 @@ static int stm32_timer_start(struct stm32_timer_trigger *priv, 0x2 << TIM_CR2_MMS_SHIFT); /* Make sure that registers are updated */ - regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); + regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG); /* Enable controller */ - regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN); + regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); mutex_unlock(&priv->lock); return 0; @@ -189,19 +189,19 @@ static void stm32_timer_stop(struct stm32_timer_trigger *priv, mutex_lock(&priv->lock); /* Stop timer */ - regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0); - regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); + regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE); + regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); regmap_write(priv->regmap, TIM_PSC, 0); regmap_write(priv->regmap, TIM_ARR, 0); /* Force disable master mode */ if (stm32_timer_is_trgo2_name(trig->name)) - regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0); + regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2); else - regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0); + regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS); /* Make sure that registers are updated */ - regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); + regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG); if (priv->enabled) { priv->enabled = false; @@ -498,11 +498,9 @@ static int stm32_counter_write_raw(struct iio_dev *indio_dev, priv->enabled = true; clk_enable(priv->clk); } - regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, - TIM_CR1_CEN); + regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); } else { - regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, - 0); + regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); if (priv->enabled) { priv->enabled = false; clk_disable(priv->clk); @@ -555,7 +553,7 @@ static int stm32_set_trigger_mode(struct iio_dev *indio_dev, { struct stm32_timer_trigger *priv = iio_priv(indio_dev); - regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, TIM_SMCR_SMS); + regmap_set_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS); return 0; } @@ -683,7 +681,7 @@ static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev, return ret; /* TIMx_ARR register shouldn't be buffered (ARPE=0) */ - regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0); + regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE); regmap_write(priv->regmap, TIM_ARR, preset); return len; @@ -757,9 +755,9 @@ static void stm32_timer_detect_trgo2(struct stm32_timer_trigger *priv) * Master mode selection 2 bits can only be written and read back when * timer supports it. */ - regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, TIM_CR2_MMS2); + regmap_set_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2); regmap_read(priv->regmap, TIM_CR2, &val); - regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0); + regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2); priv->has_trgo2 = !!val; } @@ -820,7 +818,7 @@ static void stm32_timer_trigger_remove(struct platform_device *pdev) /* Check if nobody else use the timer, then disable it */ regmap_read(priv->regmap, TIM_CCER, &val); if (!(val & TIM_CCER_CCXE)) - regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); + regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); if (priv->enabled) clk_disable(priv->clk); @@ -841,7 +839,7 @@ static int stm32_timer_trigger_suspend(struct device *dev) regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr); /* Disable the timer */ - regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); + regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); clk_disable(priv->clk); }