diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts
index 6730c44642d2910d42ec0c4adf49fefc3514dbec..e40206192ac0f7b80da23e629aa3044c04f7e969 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts
@@ -129,6 +129,27 @@ vddcpu: regulator-vddcpu {
 				<699000 98>,
 				<689000 100>;
 	};
+
+	cvbs-connector {
+		compatible = "composite-video-connector";
+
+		port {
+			cvbs_connector_in: endpoint {
+				remote-endpoint = <&cvbs_vdac_out>;
+			};
+		};
+	};
+
+	hdmi-connector {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_connector_in: endpoint {
+				remote-endpoint = <&hdmi_tx_tmds_out>;
+			};
+		};
+	};
 };
 
 &pwm_ef {
@@ -235,3 +256,21 @@ &ethmac {
 	phy-handle = <&internal_ephy>;
 	phy-mode = "rmii";
 };
+
+&cvbs_vdac_port {
+	cvbs_vdac_out: endpoint {
+		remote-endpoint = <&cvbs_connector_in>;
+	};
+};
+
+&hdmi_tx_tmds_port {
+	hdmi_tx_tmds_out: endpoint {
+		remote-endpoint = <&hdmi_connector_in>;
+	};
+};
+
+&hdmi_tx {
+	status = "okay";
+	pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+	pinctrl-names = "default";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
index 957577d986c0675a503115e1ccbc4387c2051620..ce4a24f0880c09cf4fd06d2046b520335d62a6cd 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/gpio/meson-s4-gpio.h>
 #include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
 #include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>
+#include <dt-bindings/reset/amlogic,meson-s4-reset.h>
 #include <dt-bindings/power/meson-s4-power.h>
 #include <dt-bindings/reset/amlogic,meson-s4-reset.h>
 
@@ -102,6 +103,50 @@ apb4: bus@fe000000 {
 			#size-cells = <2>;
 			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
 
+			dmc: bus@36000 {
+				compatible = "simple-bus";
+				#address-cells = <2>;
+				#size-cells = <2>;
+				ranges = <0x0 0x0 0x0 0x36000 0x0 0x2000>;
+
+				canvas: video-lut@48 {
+					compatible = "amlogic,canvas";
+					reg = <0x0 0x48 0x0 0x14>;
+				};
+			};
+
+			hdmi_tx: hdmi-tx@300000 {
+				compatible = "amlogic,meson-s4-dw-hdmi";
+				reg = <0x0 0x300000 0x0 0x10000>;
+				interrupts = <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>;
+				resets = <&reset RESET_HDMITX_APB>,
+					 <&reset RESET_HDMITXPHY>,
+					 <&reset RESET_HDMI_TX>;
+				reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
+				clocks = <&clkc_periphs CLKID_HDMI>,
+					 <&clkc_periphs CLKID_HDMITX_APB>,
+					 <&clkc_periphs CLKID_VPU_INTR>;
+				clock-names = "isfr", "iahb", "venci";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				#sound-dai-cells = <0>;
+				status = "disabled";
+
+				/* VPU VENC Input */
+				hdmi_tx_venc_port: port@0 {
+					reg = <0>;
+
+					hdmi_tx_in: endpoint {
+						remote-endpoint = <&hdmi_tx_out>;
+					};
+				};
+
+				/* TMDS Output */
+				hdmi_tx_tmds_port: port@1 {
+					reg = <1>;
+				};
+			};
+
 			clkc_periphs: clock-controller@0 {
 				compatible = "amlogic,s4-peripherals-clkc";
 				reg = <0x0 0x0 0x0 0x49c>;
@@ -584,6 +629,24 @@ mux {
 					};
 				};
 
+				hdmitx_hpd_pins: hdmitx-hpd {
+					mux {
+						groups = "hdmitx_hpd_in";
+						function = "hdmitx";
+						bias-disable;
+					};
+				};
+
+				hdmitx_ddc_pins: hdmitx-ddc {
+					mux {
+						groups = "hdmitx_sda",
+								"hdmitx_sck";
+						function = "hdmitx";
+						bias-disable;
+						drive-strength-microamp = <4000>;
+					};
+				};
+
 			};
 
 			gpio_intc: interrupt-controller@4080 {
@@ -848,5 +911,63 @@ emmc: mmc@fe08c000 {
 			no-sd;
 			status = "disabled";
 		};
+
+		vpu: vpu@ff000000 {
+			compatible = "amlogic,meson-s4-vpu";
+			reg = <0x0 0xff000000 0x0 0x40000>,
+				  <0x0 0xfe008000 0x0 0x2000>,
+				  <0x0 0xfe000000 0x0 0x2000>,
+				  <0x0 0xfe00c000 0x0 0x0800>,
+				  <0x0 0xfe010000 0x0 0x0100>;
+			reg-names = "vpu", "hhi", "clkctrl", "pwrctrl", "sysctrl";
+			interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			amlogic,canvas = <&canvas>;
+			power-domains = <&pwrc PWRC_S4_VPU_HDMI_ID>;
+
+			clocks = <&clkc_periphs CLKID_VPU>,
+				 <&clkc_periphs CLKID_VAPB>;
+			clock-names = "vpu", "vapb";
+
+			/*
+			 * VPU clocking is provided by two identical clock paths
+			 * VPU_0 and VPU_1 muxed to a single clock by a glitch
+			 * free mux to safely change frequency while running.
+			 * Same for VAPB but with a final gate after the glitch free mux.
+			 */
+			assigned-clocks = <&clkc_periphs CLKID_VPU_0_SEL>,
+					  <&clkc_periphs CLKID_VPU_0>,
+					  <&clkc_periphs CLKID_VPU>, /* Glitch free mux */
+					  <&clkc_periphs CLKID_VAPB_0_SEL>,
+					  <&clkc_periphs CLKID_VAPB_0>,
+					  <&clkc_periphs CLKID_VAPB>; /* Glitch free mux */
+			assigned-clock-parents = <&clkc_periphs CLKID_FCLK_DIV3>,
+						 <0>, /* Do Nothing */
+						 <&clkc_periphs CLKID_VPU_0>,
+						 <&clkc_periphs CLKID_FCLK_DIV4>,
+						 <0>, /* Do Nothing */
+						 <&clkc_periphs CLKID_VAPB_0>;
+			assigned-clock-rates = <0>, /* Do Nothing */
+					       <666666666>,
+					       <0>, /* Do Nothing */
+					       <0>, /* Do Nothing */
+					       <250000000>,
+					       <0>; /* Do Nothing */
+
+			/* CVBS VDAC output port */
+			cvbs_vdac_port: port@0 {
+				reg = <0>;
+			};
+
+			/* HDMI-TX output port */
+			hdmi_tx_port: port@1 {
+				reg = <1>;
+
+				hdmi_tx_out: endpoint {
+					remote-endpoint = <&hdmi_tx_in>;
+				};
+			};
+		};
 	};
 };
