[2/4] irqchip: Add support for Amlogic A4 and A5 SoCs

Commit Message

Xianwei Zhao via B4 Relay Feb. 19, 2025, 7:29 a.m. UTC

From: Xianwei Zhao <[e-mail]>

The Amlogic A4 SoCs support 12 GPIO IRQ lines and 2 AO GPIO IRQ lines,
A5 SoCs support 12 GPIO IRQ lines, details are as below.

A4 IRQ Number:
- 72:55   18 pins on bank T
- 54:32   23 pins on bank X
- 31:16   16 pins on bank D
- 15:14    2 pins on bank E
- 13:0    14 pins on bank B

A4 AO IRQ Number:
- 7       1 pin  on bank TESTN
- 6:0     7 pins on bank AO

A5 IRQ Number:
- 98      1 pin  on bank TESTN
- 97:82   16 pins on bank Z
- 81:62   20 pins on bank X
- 61:48   14 pins on bank T
- 47:32   16 pins on bank D
- 31:27    5 pins on bank H
- 26:25    2 pins on bank E
- 24:14   11 pins on bank C
- 13:0    14 pins on bank B

Signed-off-by: Xianwei Zhao <[e-mail]>
---
 drivers/irqchip/irq-meson-gpio.c | 61 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)

Comments

Thomas Gleixner Feb. 21, 2025, 9:07 a.m. UTC | #1

On Wed, Feb 19 2025 at 15:29, Xianwei Zhao via wrote:
>  
> +static int meson_ao_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
> +				      unsigned int type, u32 *channel_hwirq)
> +{
> +	u32 val = 0;
> +	unsigned int idx;
> +
> +	idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
> +
> +	type &= IRQ_TYPE_SENSE_MASK;
> +
> +	meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_AO, BIT(idx), 0);
> +
> +	if (type == IRQ_TYPE_EDGE_BOTH) {
> +		val |= BIT(ctl->params->edge_both_offset + (idx));
> +		meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_AO,
> +					   BIT(ctl->params->edge_both_offset + (idx)), val);
> +		return 0;
> +	}
> +
> +	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
> +		val |= BIT(ctl->params->pol_low_offset + idx);
> +
> +	if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
> +		val |= BIT(ctl->params->edge_single_offset + idx);
> +
> +	meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
> +				   BIT(idx) | BIT(12 + idx), val);
> +
> +	return 0;
> +};

This function is a full copy of meson_s4_gpio_irq_set_type() with the
only difference of:

           s/REG_EDGE_POL_S4/REG_EDGE_POL_AO/

Can you please stick that register offset into the parameter structure
and use the function for both variants?

Thanks,

        tglx

Xianwei Zhao Feb. 21, 2025, 9:40 a.m. UTC | #2

Hi Thomas,
    Thank you for your advice.

On 2025/2/21 17:07, Thomas Gleixner wrote:
> [You don't often get email from [e-mail]. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> 
> [ EXTERNAL EMAIL ]
> 
> On Wed, Feb 19 2025 at 15:29, Xianwei Zhao via wrote:
>>
>> +static int meson_ao_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
>> +                                   unsigned int type, u32 *channel_hwirq)
>> +{
>> +     u32 val = 0;
>> +     unsigned int idx;
>> +
>> +     idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
>> +
>> +     type &= IRQ_TYPE_SENSE_MASK;
>> +
>> +     meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_AO, BIT(idx), 0);
>> +
>> +     if (type == IRQ_TYPE_EDGE_BOTH) {
>> +             val |= BIT(ctl->params->edge_both_offset + (idx));
>> +             meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_AO,
>> +                                        BIT(ctl->params->edge_both_offset + (idx)), val);
>> +             return 0;
>> +     }
>> +
>> +     if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
>> +             val |= BIT(ctl->params->pol_low_offset + idx);
>> +
>> +     if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
>> +             val |= BIT(ctl->params->edge_single_offset + idx);
>> +
>> +     meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
>> +                                BIT(idx) | BIT(12 + idx), val);
>> +
>> +     return 0;
>> +};
> 
> This function is a full copy of meson_s4_gpio_irq_set_type() with the
> only difference of:
> 
>             s/REG_EDGE_POL_S4/REG_EDGE_POL_AO/
> 
> Can you please stick that register offset into the parameter structure
> and use the function for both variants?
> 
> Thanks,
> 

Will do.

>          tglx

Patch

diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index cd789fa51519..1ef391274653 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -28,6 +28,8 @@ 
 #define REG_PIN_A1_SEL	0x04
 /* Used for s4 chips */
 #define REG_EDGE_POL_S4	0x1c
+/* Used for A4 AO chips */
+#define REG_EDGE_POL_AO	0x08
 
 /*
  * Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by
@@ -57,6 +59,8 @@  static int meson8_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
 				    unsigned int type, u32 *channel_hwirq);
 static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
 				      unsigned int type, u32 *channel_hwirq);
+static int meson_ao_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
+				      unsigned int type, u32 *channel_hwirq);
 
 struct irq_ctl_ops {
 	void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
@@ -105,6 +109,17 @@  struct meson_gpio_irq_params {
 	.pin_sel_mask = 0x7f,					\
 	.nr_channels = 8,					\
 
+#define INIT_MESON_A4_AO_COMMON_DATA(irqs)			\
+	INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init,		\
+			  meson_a1_gpio_irq_sel_pin,		\
+			  meson_ao_gpio_irq_set_type)		\
+	.support_edge_both = true,				\
+	.edge_both_offset = 0,					\
+	.edge_single_offset = 12,				\
+	.pol_low_offset = 0,					\
+	.pin_sel_mask = 0xff,					\
+	.nr_channels = 2,					\
+
 #define INIT_MESON_S4_COMMON_DATA(irqs)				\
 	INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init,		\
 			  meson_a1_gpio_irq_sel_pin,		\
@@ -146,6 +161,18 @@  static const struct meson_gpio_irq_params a1_params = {
 	INIT_MESON_A1_COMMON_DATA(62)
 };
 
+static const struct meson_gpio_irq_params a4_params = {
+	INIT_MESON_S4_COMMON_DATA(81)
+};
+
+static const struct meson_gpio_irq_params a4_ao_params = {
+	INIT_MESON_A4_AO_COMMON_DATA(8)
+};
+
+static const struct meson_gpio_irq_params a5_params = {
+	INIT_MESON_S4_COMMON_DATA(99)
+};
+
 static const struct meson_gpio_irq_params s4_params = {
 	INIT_MESON_S4_COMMON_DATA(82)
 };
@@ -168,6 +195,9 @@  static const struct of_device_id meson_irq_gpio_matches[] __maybe_unused = {
 	{ .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params },
 	{ .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params },
 	{ .compatible = "amlogic,meson-s4-gpio-intc", .data = &s4_params },
+	{ .compatible = "amlogic,a4-gpio-ao-intc", .data = &a4_ao_params },
+	{ .compatible = "amlogic,a4-gpio-intc", .data = &a4_params },
+	{ .compatible = "amlogic,a5-gpio-intc", .data = &a5_params },
 	{ .compatible = "amlogic,c3-gpio-intc", .data = &c3_params },
 	{ .compatible = "amlogic,t7-gpio-intc", .data = &t7_params },
 	{ }
@@ -383,6 +413,37 @@  static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
 	return 0;
 };
 
+static int meson_ao_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
+				      unsigned int type, u32 *channel_hwirq)
+{
+	u32 val = 0;
+	unsigned int idx;
+
+	idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
+
+	type &= IRQ_TYPE_SENSE_MASK;
+
+	meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_AO, BIT(idx), 0);
+
+	if (type == IRQ_TYPE_EDGE_BOTH) {
+		val |= BIT(ctl->params->edge_both_offset + (idx));
+		meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_AO,
+					   BIT(ctl->params->edge_both_offset + (idx)), val);
+		return 0;
+	}
+
+	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
+		val |= BIT(ctl->params->pol_low_offset + idx);
+
+	if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
+		val |= BIT(ctl->params->edge_single_offset + idx);
+
+	meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
+				   BIT(idx) | BIT(12 + idx), val);
+
+	return 0;
+};
+
 static unsigned int meson_gpio_irq_type_output(unsigned int type)
 {
 	unsigned int sense = type & IRQ_TYPE_SENSE_MASK;