diff mbox series

drm/meson: fix green/pink color distortion from HDR set during vendor Uboot

Message ID 553e127c-9839-d15b-d435-c01f18c7be48@gmail.com (mailing list archive)
State New
Delegated to: Neil Armstrong
Headers show
Series drm/meson: fix green/pink color distortion from HDR set during vendor Uboot | expand

Commit Message

Mathias Steiger April 27, 2021, 11:11 p.m. UTC
Fixes: 728883948b0d ("drm/meson: Add G12A Support for VIU setup")

Tested-by: Neil Armstrong<narmstrong@baylibre.com>

Comments

Neil Armstrong May 20, 2021, 2:04 p.m. UTC | #1
Hi Mathias,

On 28/04/2021 01:11, Mathias Steiger wrote:
> 
> Fixes: 728883948b0d ("drm/meson: Add G12A Support for VIU setup")
> 
> Tested-by: Neil Armstrong<narmstrong@baylibre.com>

The formatting is wrong, but I'll reformat it before applying it, but I need to confirm you sign-off this patch
with something like "Signed-off: Mathias Steiger <mathias.steiger@googlemail.com>" for my to apply it.

Thanks,

Neil

> 
> 
> diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h
> --- a/drivers/gpu/drm/meson/meson_registers.h
> +++ b/drivers/gpu/drm/meson/meson_registers.h
> @@ -634,6 +634,11 @@
>  #define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2 0x3dbc
>  #define VPP_WRAP_OSD3_MATRIX_EN_CTRL 0x3dbd
>  
> +/* osd1 HDR */
> +#define OSD1_HDR2_CTRL 0x38a0
> +#define OSD1_HDR2_CTRL_VDIN0_HDR2_TOP_EN       BIT(13)
> +#define OSD1_HDR2_CTRL_REG_ONLY_MAT            BIT(16)
> +
>  /* osd2 scaler */
>  #define OSD2_VSC_PHASE_STEP 0x3d00
>  #define OSD2_VSC_INI_PHASE 0x3d01
> diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c
> --- a/drivers/gpu/drm/meson/meson_viu.c
> +++ b/drivers/gpu/drm/meson/meson_viu.c
> @@ -426,8 +426,14 @@ void meson_viu_init(struct meson_drm *priv)
>             meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
>                 meson_viu_load_matrix(priv);
>         else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
> +       {
>                 meson_viu_set_g12a_osd1_matrix(priv, RGB709_to_YUV709l_coeff,
>                                                true);
> +               /* fix green/pink color distortion from vendor uboot */
> +               writel_bits_relaxed(OSD1_HDR2_CTRL_REG_ONLY_MAT |
> +                                   OSD1_HDR2_CTRL_VDIN0_HDR2_TOP_EN, 0,
> +                                   priv->io_base + _REG(OSD1_HDR2_CTRL));
> +       }
>  
>         /* Initialize OSD1 fifo control register */
>         reg = VIU_OSD_DDR_PRIORITY_URGENT |
> 
> 
> _______________________________________________
> linux-amlogic mailing list
> linux-amlogic@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic
diff mbox series

Patch

diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h
--- a/drivers/gpu/drm/meson/meson_registers.h
+++ b/drivers/gpu/drm/meson/meson_registers.h
@@ -634,6 +634,11 @@ 
  #define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2 0x3dbc
  #define VPP_WRAP_OSD3_MATRIX_EN_CTRL 0x3dbd
  
+/* osd1 HDR */
+#define OSD1_HDR2_CTRL 0x38a0
+#define OSD1_HDR2_CTRL_VDIN0_HDR2_TOP_EN       BIT(13)
+#define OSD1_HDR2_CTRL_REG_ONLY_MAT            BIT(16)
+
  /* osd2 scaler */
  #define OSD2_VSC_PHASE_STEP 0x3d00
  #define OSD2_VSC_INI_PHASE 0x3d01
diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c
--- a/drivers/gpu/drm/meson/meson_viu.c
+++ b/drivers/gpu/drm/meson/meson_viu.c
@@ -426,8 +426,14 @@  void meson_viu_init(struct meson_drm *priv)
             meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
                 meson_viu_load_matrix(priv);
         else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
+       {
                 meson_viu_set_g12a_osd1_matrix(priv, RGB709_to_YUV709l_coeff,
                                                true);
+               /* fix green/pink color distortion from vendor uboot */
+               writel_bits_relaxed(OSD1_HDR2_CTRL_REG_ONLY_MAT |
+                                   OSD1_HDR2_CTRL_VDIN0_HDR2_TOP_EN, 0,
+                                   priv->io_base + _REG(OSD1_HDR2_CTRL));
+       }
  
         /* Initialize OSD1 fifo control register */
         reg = VIU_OSD_DDR_PRIORITY_URGENT |