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[v9,00/14] Update SMMUv3 to the modern iommu API (part 2b/3)

Message ID 0-v9-5cd718286059+79186-smmuv3_newapi_p2b_jgg@nvidia.com (mailing list archive)
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Series Update SMMUv3 to the modern iommu API (part 2b/3) | expand

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Jason Gunthorpe June 25, 2024, 12:37 p.m. UTC 
Continuing the work of part 1 and 2a this part focuses on the PASID and
SVA code bringing these functional improvements:

 - attach_dev failure does not change the HW configuration.

 - Full PASID API support including:
    - S1/SVA domains attached to PASIDs
    - IDENTITY/BLOCKED/S1 attached to RID
    - Change of the RID domain while PASIDs are attached

 - Streamlined SVA support using the core infrastructure

 - Hitless, whenever possible, change between two domains

This requires some reorganizing how the invalidation is tracked, a
flexible linked list containing the SSIDs as well as the ATC information
is used instead of a single master.

The revised invalidation infrastructure is used to build generic support
for attaching any sort of domain to any SSID, including the necessary
maintenance of the invalidation list and the global ATS state. This
mechansim is used again in part 3 as part of the nesting series.

The ATS ordering is generalized and consolidated so that the PASID flow
can use it and put into a form where it is fully hitless, whenever
possible. This is necessary as changes to single PASIDs or RIDs can not
change global state like ATS without impacting other, still attached,
PASIDs or RIDs.

Next simply replace the entire outdated SVA mmu_notifier implementation in
one shot and switch it over to the newly created generic PASID layer and
generic invalidation logic. This avoids the messy and confusing approach
of trying to incrementally untangle this in place. The new code is small
and simple enough this is much better than trying to figure out smaller
steps.

Once SVA is resting on the consolidate PASID layer it is straightforward
to make the PASID interface functionally complete by supporting S1DSS to
allow concurrent change of the RID while a PASID is attached and allow
supporting PASID over an IDENTIY RID.

This continues to support lazy allocation and installation of the CD table
by continuing to use the CFG mode for IDENTITY/BLOCKED when when the PASID
table is empty.

Finally enable attaching any S1 domain to a PASID, not just SVA.

It achieves the same goals as the several series from Michael and the
S1DSS series from Nicolin that were trying to improve portions of the API.

This is on github:
https://github.com/jgunthorpe/linux/commits/smmuv3_newapi

v9:
 - Clarify comments
 - Collect tags
v8: https://lore.kernel.org/r/0-v8-6f85cdc10ce7+563e-smmuv3_newapi_p2b_jgg@nvidia.com
 - Rebase on v6.10-rc2
 - Make arm_smmu_sva_domain_alloc NULL when SVA is disabled so the core
   code sees a NULL function pointer
 - Update comments around arm_smmu_attach_prepare()
 - Rename struct attach_state -> arm_smmu_attach_state and document
   better, include more common function paramters in state
 - Consistently use ats_enabled everywhere, replacing disable_ats in state
 - Move the note about ATS bypass/abort to arm_smmu_attach_prepare()
 - Remove temporary cd_table.in_ste check in arm_smmu_sva_set_dev_pasid()
 - Improve comments and clarity of logic in arm_smmu_attach_commit()
 - Shorten arm_smmu_mmu_notifier_free()
 - Fix domain -> sid_domain typo in arm_smmu_remove_dev_pasid()
v7: https://lore.kernel.org/r/0-v7-9597c885796c+d2-smmuv3_newapi_p2b_jgg@nvidia.com
 - Second half of the split series
 - Rebase on Joerg's latest
 - Accommodate ARM_SMMU_FEAT_ATTR_TYPES_OVR for the S1DSS code
 - Include the S1DSS kunit tests
 - Include hunks to adjust the unit tests to API changes from this series
 - Move 3 BTM related patches out of this series, they can go in the BTM
   enablement series.
 - Move the domain_alloc_sva() conversion to the first patch, and rebase
   on the accepted core code change
 - Use the new core APIs for the PASID ops
 - Revise commit messages
v6: https://lore.kernel.org/r/0-v6-228e7adf25eb+4155-smmuv3_newapi_p2_jgg@nvidia.com

Jason Gunthorpe (14):
  iommu/arm-smmu-v3: Convert to domain_alloc_sva()
  iommu/arm-smmu-v3: Start building a generic PASID layer
  iommu/arm-smmu-v3: Make smmu_domain->devices into an allocated list
  iommu/arm-smmu-v3: Make changing domains be hitless for ATS
  iommu/arm-smmu-v3: Add ssid to struct arm_smmu_master_domain
  iommu/arm-smmu-v3: Do not use master->sva_enable to restrict attaches
  iommu/arm-smmu-v3: Thread SSID through the arm_smmu_attach_*()
    interface
  iommu/arm-smmu-v3: Make SVA allocate a normal arm_smmu_domain
  iommu/arm-smmu-v3: Keep track of arm_smmu_master_domain for SVA
  iommu/arm-smmu-v3: Put the SVA mmu notifier in the smmu_domain
  iommu/arm-smmu-v3: Allow IDENTITY/BLOCKED to be set while PASID is
    used
  iommu/arm-smmu-v3: Test the STE S1DSS functionality
  iommu/arm-smmu-v3: Allow a PASID to be set when RID is
    IDENTITY/BLOCKED
  iommu/arm-smmu-v3: Allow setting a S1 domain to a PASID

 .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c   | 431 +++-----------
 .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c  | 116 +++-
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c   | 560 ++++++++++++++----
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h   |  52 +-
 4 files changed, 663 insertions(+), 496 deletions(-)


base-commit: c3f38fa61af77b49866b006939479069cd451173

Comments

Will Deacon July 2, 2024, 6:43 p.m. UTC | #1 
On Tue, 25 Jun 2024 09:37:31 -0300, Jason Gunthorpe wrote:
> Continuing the work of part 1 and 2a this part focuses on the PASID and
> SVA code bringing these functional improvements:
> 
>  - attach_dev failure does not change the HW configuration.
> 
>  - Full PASID API support including:
>     - S1/SVA domains attached to PASIDs
>     - IDENTITY/BLOCKED/S1 attached to RID
>     - Change of the RID domain while PASIDs are attached
> 
> [...]

Applied to will (for-joerg/arm-smmu/updates), thanks!

[01/14] iommu/arm-smmu-v3: Convert to domain_alloc_sva()
        https://git.kernel.org/will/c/678d79b98028
[02/14] iommu/arm-smmu-v3: Start building a generic PASID layer
        https://git.kernel.org/will/c/85f2fb6ef413
[03/14] iommu/arm-smmu-v3: Make smmu_domain->devices into an allocated list
        https://git.kernel.org/will/c/ad10dce61303
[04/14] iommu/arm-smmu-v3: Make changing domains be hitless for ATS
        https://git.kernel.org/will/c/7497f4211f4f
[05/14] iommu/arm-smmu-v3: Add ssid to struct arm_smmu_master_domain
        https://git.kernel.org/will/c/64efb3def3a5
[06/14] iommu/arm-smmu-v3: Do not use master->sva_enable to restrict attaches
        https://git.kernel.org/will/c/be7c90de39fd
[07/14] iommu/arm-smmu-v3: Thread SSID through the arm_smmu_attach_*() interface
        https://git.kernel.org/will/c/1d5f34f0002f
[08/14] iommu/arm-smmu-v3: Make SVA allocate a normal arm_smmu_domain
        https://git.kernel.org/will/c/d7b2d2ba1b84
[09/14] iommu/arm-smmu-v3: Keep track of arm_smmu_master_domain for SVA
        https://git.kernel.org/will/c/49db2ed23c52
[10/14] iommu/arm-smmu-v3: Put the SVA mmu notifier in the smmu_domain
        https://git.kernel.org/will/c/d38c28dbefee
[11/14] iommu/arm-smmu-v3: Allow IDENTITY/BLOCKED to be set while PASID is used
        https://git.kernel.org/will/c/ce26ea9e6e12
[12/14] iommu/arm-smmu-v3: Test the STE S1DSS functionality
        https://git.kernel.org/will/c/3b5302cbb06a
[13/14] iommu/arm-smmu-v3: Allow a PASID to be set when RID is IDENTITY/BLOCKED
        https://git.kernel.org/will/c/8ee9175c2582
[14/14] iommu/arm-smmu-v3: Allow setting a S1 domain to a PASID
        https://git.kernel.org/will/c/f3b273b7c7e4

Cheers,