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[v3,0/4] Add i.MX8MQ clock driver

Message ID 1533825941-17224-1-git-send-email-abel.vesa@nxp.com (mailing list archive)
Headers show
Series Add i.MX8MQ clock driver | expand

Message

Abel Vesa Aug. 9, 2018, 2:45 p.m. UTC
This is basically just a resend of the following patchset:

https://www.spinics.net/lists/linux-clk/msg23141.html

I've just updated the patchset and implemented Shawn's
and Aisheng's comments.

I hope I haven't missed any of their comments.

Lucas Stach (4):
  dt-bindings: add binding for i.MX8MQ CCM
  clk: imx: add fractional PLL output clock
  clk: imx: add SCCG PLL type
  clk: imx: add clock driver for i.MX8MQ CCM

 .../devicetree/bindings/clock/imx8mq-clock.txt     |  20 +
 drivers/clk/imx/Makefile                           |   5 +-
 drivers/clk/imx/clk-frac-pll.c                     | 230 ++++++
 drivers/clk/imx/clk-imx8mq.c                       | 856 +++++++++++++++++++++
 drivers/clk/imx/clk-sccg-pll.c                     | 231 ++++++
 drivers/clk/imx/clk.h                              |  48 ++
 include/dt-bindings/clock/imx8mq-clock.h           | 629 +++++++++++++++
 7 files changed, 2018 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/clock/imx8mq-clock.txt
 create mode 100644 drivers/clk/imx/clk-frac-pll.c
 create mode 100644 drivers/clk/imx/clk-imx8mq.c
 create mode 100644 drivers/clk/imx/clk-sccg-pll.c
 create mode 100644 include/dt-bindings/clock/imx8mq-clock.h

Comments

Sascha Hauer Aug. 10, 2018, 6:03 a.m. UTC | #1
Hi Abel,

On Thu, Aug 09, 2018 at 05:45:37PM +0300, Abel Vesa wrote:
> This is basically just a resend of the following patchset:
> 
> https://www.spinics.net/lists/linux-clk/msg23141.html
> 
> I've just updated the patchset and implemented Shawn's
> and Aisheng's comments.
> 
> I hope I haven't missed any of their comments.

I think what I said to v2 back in march still stays valid:

> A general thought: The i.MX8M finally has a consistent clock tree. We
> have for example 70 Peripheral clock slices consisting of a mux, a gate
> and two dividers, all 70 looking the same.
> For these it might make sense to create a more complex clock type
> providing mux, gate and set rate functionality in one clock. This would
> drastically reduce the number of clocks we have to handle.

Sascha