| Message ID | 1538278348-7716-1-git-send-email-Anson.Huang@nxp.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add i.MX6ULZ SoC support | expand |
On Sun, Sep 30, 2018 at 11:32:25AM +0800, Anson Huang wrote: > This patch set adds i.MX6ULZ SoC support, i.MX6ULZ is a new SoC of > i.MX6 family, compared to i.MX6ULL, it removes below modules: > > - UART5/UART6/UART7/UART8; > - PWM5/PWM6/PWM7/PWM8; > - eCSPI3/eCSPI4; > - CAN1/CAN2; > - FEC1/FEC2; > - I2C3/I2C4; > - EPIT2; > - LCDIF; > - GPT2; > - TSC; > > And i.MX6ULZ has same soc_id as i.MX6ULL, but SRC_SBMR2 bit[6] is > to differentiate i.MX6ULZ from i.MX6ULL, 1'b1 means i.MX6ULZ and > 1'b0 means i.MX6ULL. i.MX6ULZ reuse most of i.MX6UL/i.MX6ULL code, > just add the new CPU type and remove those non-exist modules from dtb. > > Anson Huang (3): > ARM: imx: add i.mx6ulz msl support > dt-bindings: arm: add compatible for i.MX6ULZ 14x14 EVK board > ARM: dts: imx: add i.mx6ulz and i.mx6ulz 14x14 evk support Applied all, thanks.
On 30.09.18 09:33, Shawn Guo wrote: > On Sun, Sep 30, 2018 at 11:32:25AM +0800, Anson Huang wrote: >> This patch set adds i.MX6ULZ SoC support, i.MX6ULZ is a new SoC of >> i.MX6 family, compared to i.MX6ULL, it removes below modules: >> >> - UART5/UART6/UART7/UART8; >> - PWM5/PWM6/PWM7/PWM8; >> - eCSPI3/eCSPI4; >> - CAN1/CAN2; >> - FEC1/FEC2; >> - I2C3/I2C4; >> - EPIT2; >> - LCDIF; >> - GPT2; >> - TSC; >> >> And i.MX6ULZ has same soc_id as i.MX6ULL, but SRC_SBMR2 bit[6] is >> to differentiate i.MX6ULZ from i.MX6ULL, 1'b1 means i.MX6ULZ and >> 1'b0 means i.MX6ULL. i.MX6ULZ reuse most of i.MX6UL/i.MX6ULL code, >> just add the new CPU type and remove those non-exist modules from dtb. >> >> Anson Huang (3): >> ARM: imx: add i.mx6ulz msl support >> dt-bindings: arm: add compatible for i.MX6ULZ 14x14 EVK board >> ARM: dts: imx: add i.mx6ulz and i.mx6ulz 14x14 evk support > > Applied all, thanks. I'm currently starting work on an i.MX6ULZ custom port, which will use the EIM interface. While starting the pin-mux configuration for this board, I noticed that the pinfunc defines available for MX6UL (imx6ul-pinfunc.h which is used for i.MX6ULL/ULZ as well AFAICT) does not match the reference manual descriptions for the EIM pin muxing. One example: i.MX6UL: EIM_DATA00 is available on pad LCD_DATA08 i.MX6ULZ: EIM_DATA00 is available on pad GPIO3_IO13 ... My question now: Is a i.MX6ULL/ULZ specific pinfunc.h header available in any (NXP?) downstream Linux repository? Thanks, Stefan
On 22.01.20 09:39, Stefan Roese wrote: <snip> > I'm currently starting work on an i.MX6ULZ custom port, which will use > the EIM interface. While starting the pin-mux configuration for this > board, I noticed that the pinfunc defines available for MX6UL > (imx6ul-pinfunc.h which is used for i.MX6ULL/ULZ as well AFAICT) does > not match the reference manual descriptions for the EIM pin muxing. > One example: > > i.MX6UL: EIM_DATA00 is available on pad LCD_DATA08 > i.MX6ULZ: EIM_DATA00 is available on pad GPIO3_IO13 > ... > > My question now: Is a i.MX6ULL/ULZ specific pinfunc.h header available > in any (NXP?) downstream Linux repository? Answering my own question: I missed the already available mx6ull specific pinfunc.h header, sorry: arch/arm/boot/dts/imx6ull-pinfunc.h But this file is missing the EIM definitions for the MX6ULL/ULZ. Before adding them myself, are these available in any downstream repository? Thanks, Stefan
Hi Stefan, On Wed, Jan 22, 2020 at 8:53 AM Stefan Roese <sr@denx.de> wrote: > Answering my own question: I missed the already available mx6ull specific > pinfunc.h header, sorry: > > arch/arm/boot/dts/imx6ull-pinfunc.h > > But this file is missing the EIM definitions for the MX6ULL/ULZ. Before > adding them myself, are these available in any downstream repository? I don't see the EIM definitions in the NXP kernel either: https://source.codeaurora.org/external/imx/linux-imx/tree/arch/arm/boot/dts/imx6ull-pinfunc.h?h=imx_5.4.0_8dxlphantom_er Regards, Fabio Estevam
This patch set adds i.MX6ULZ SoC support, i.MX6ULZ is a new SoC of i.MX6 family, compared to i.MX6ULL, it removes below modules: - UART5/UART6/UART7/UART8; - PWM5/PWM6/PWM7/PWM8; - eCSPI3/eCSPI4; - CAN1/CAN2; - FEC1/FEC2; - I2C3/I2C4; - EPIT2; - LCDIF; - GPT2; - TSC; And i.MX6ULZ has same soc_id as i.MX6ULL, but SRC_SBMR2 bit[6] is to differentiate i.MX6ULZ from i.MX6ULL, 1'b1 means i.MX6ULZ and 1'b0 means i.MX6ULL. i.MX6ULZ reuse most of i.MX6UL/i.MX6ULL code, just add the new CPU type and remove those non-exist modules from dtb. Anson Huang (3): ARM: imx: add i.mx6ulz msl support dt-bindings: arm: add compatible for i.MX6ULZ 14x14 EVK board ARM: dts: imx: add i.mx6ulz and i.mx6ulz 14x14 evk support Documentation/devicetree/bindings/arm/fsl.txt | 4 +++ arch/arm/boot/dts/Makefile | 3 ++- arch/arm/boot/dts/imx6ulz-14x14-evk.dts | 20 ++++++++++++++ arch/arm/boot/dts/imx6ulz.dtsi | 38 +++++++++++++++++++++++++++ arch/arm/mach-imx/anatop.c | 20 ++++++++++++++ arch/arm/mach-imx/cpu.c | 3 +++ arch/arm/mach-imx/mxc.h | 7 +++++ arch/arm/mach-imx/pm-imx6.c | 4 +-- 8 files changed, 96 insertions(+), 3 deletions(-) create mode 100644 arch/arm/boot/dts/imx6ulz-14x14-evk.dts create mode 100644 arch/arm/boot/dts/imx6ulz.dtsi