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Mon, 20 May 2019 17:27:18 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 1860734; Mon, 20 May 2019 15:27:15 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node1.st.com [10.75.127.13]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id AEEE12BAC; Mon, 20 May 2019 15:27:15 +0000 (GMT) Received: from SFHDAG5NODE1.st.com (10.75.127.13) by SFHDAG5NODE1.st.com (10.75.127.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Mon, 20 May 2019 17:27:15 +0200 Received: from SFHDAG5NODE1.st.com ([fe80::cc53:528c:36c8:95f6]) by SFHDAG5NODE1.st.com ([fe80::cc53:528c:36c8:95f6%20]) with mapi id 15.00.1347.000; Mon, 20 May 2019 17:27:15 +0200 From: Gerald BAEZA To: "will.deacon@arm.com" , "mark.rutland@arm.com" , "robh+dt@kernel.org" , "mcoquelin.stm32@gmail.com" , Alexandre TORGUE , "corbet@lwn.net" , "linux@armlinux.org.uk" , "olof@lixom.net" , "horms+renesas@verge.net.au" , "arnd@arndb.de" Subject: [PATCH v2 0/5] stm32-ddr-pmu driver creation Thread-Topic: [PATCH v2 0/5] stm32-ddr-pmu driver creation Thread-Index: AQHVDyCA+bIWujGZrUGYoRHYm+G4Sg== Date: Mon, 20 May 2019 15:27:15 +0000 Message-ID: <1558366019-24214-1-git-send-email-gerald.baeza@st.com> Accept-Language: fr-FR, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.75.127.45] MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-20_07:, , signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190520_082741_009520_3368A703 X-CRM114-Status: GOOD ( 14.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "devicetree@vger.kernel.org" , "linux-doc@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Gerald BAEZA , "linux-stm32@st-md-mailman.stormreply.com" , "linux-arm-kernel@lists.infradead.org" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The DDRPERFM is the DDR Performance Monitor embedded in STM32MP1 SOC. This series adds support for the DDRPERFM via a new stm32-ddr-pmu driver, registered into the perf framework. This driver is inspired from arch/arm/mm/cache-l2x0-pmu.c --- Changes from v1: - add 'resets' description (bindings) and using (driver). Thanks Rob. - rebase on 5.2-rc1 (that includes the ddrperfm clock control patch). Gerald Baeza (5): Documentation: perf: stm32: ddrperfm support dt-bindings: perf: stm32: ddrperfm support perf: stm32: ddrperfm driver creation ARM: configs: enable STM32_DDR_PMU ARM: dts: stm32: add ddrperfm on stm32mp157c .../devicetree/bindings/perf/stm32-ddr-pmu.txt | 20 + Documentation/perf/stm32-ddr-pmu.txt | 41 ++ arch/arm/boot/dts/stm32mp157c.dtsi | 9 + arch/arm/configs/multi_v7_defconfig | 1 + drivers/perf/Kconfig | 6 + drivers/perf/Makefile | 1 + drivers/perf/stm32_ddr_pmu.c | 512 +++++++++++++++++++++ 7 files changed, 590 insertions(+) create mode 100644 Documentation/devicetree/bindings/perf/stm32-ddr-pmu.txt create mode 100644 Documentation/perf/stm32-ddr-pmu.txt create mode 100644 drivers/perf/stm32_ddr_pmu.c