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Mon, 4 Nov 2019 08:10:21 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.85.251) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Mon, 4 Nov 2019 08:10:18 -0700 From: Claudiu Beznea To: , , , , , , Subject: [PATCH v2 0/2] add Microchip PIT64B timer Date: Mon, 4 Nov 2019 17:10:02 +0200 Message-ID: <1572880204-4514-1-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191104_071041_635709_6786FF0C X-CRM114-Status: GOOD ( 10.21 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.153.233 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Claudiu Beznea Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Hi, This series adds driver for Microchip PIT64B timer. Timer could be used in continuous or oneshot mode. It has 2x32 bit registers to emulate a 64 bit timer. The timer's period could be configured via LSB_PR and MSB_PR registers. The current timer's value could be checked via TLSB and TMSB registers. When (TMSB << 32) | TLSB value reach the (MSB_PR << 32) | LSB_PR interrupt is raised. If in contiuous mode the TLSB and TMSB resets and restart counting. This drivers uses PIT64B capabilities for clocksource and clockevent. The first requested PIT64B timer is used for clockevent. The second one is used for clocksource. Individual PIT64B hardware resources were used for clocksource and clockevent to be able to support high resolution timers with this PIT64B implementation. Thank you, Claudiu Beznea Changes in v2: - remove clock-frequency DT binding and hardcoded it in the driver - initialize best_pres variable in mchp_pit64b_pres_prepare() - remove MCHP_PIT64B_DEF_FREQ - get rid of patches 3-5 from v1 [1] since there is no entry in MAINTAINERS file for this entry. It was removed in commit 44015a8181a5 ("MAINTAINERS: at91: remove the TC entry") [1] https://lore.kernel.org/lkml/1552580772-8499-1-git-send-email-claudiu.beznea@microchip.com/ Claudiu Beznea (2): dt-bindings: arm: atmel: add bindings for PIT64B clocksource/drivers/timer-microchip-pit64b: add Microchip PIT64B support .../devicetree/bindings/arm/atmel-sysregs.txt | 6 + drivers/clocksource/Kconfig | 6 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-microchip-pit64b.c | 462 +++++++++++++++++++++ 4 files changed, 475 insertions(+) create mode 100644 drivers/clocksource/timer-microchip-pit64b.c