[0/2] at91-sama5d2_shdwc shutdown controller

Message

Claudiu Beznea Dec. 19, 2019, 2:27 p.m. UTC

PMC master clock register offset is different b/w sam9x60 and
other SoCs. Since there is a need of this register offset in
shutdown procedure we need to have it per SoC. This is what
this series does.

Claudiu Beznea (2):
  power: reset: at91-sama5d2_shdwc: introduce struct shdwc_reg_config
  power: reset: at91-sama5d2_shdwc: use proper master clock register
    offset

 drivers/power/reset/at91-sama5d2_shdwc.c | 75 +++++++++++++++++++++-----------
 1 file changed, 49 insertions(+), 26 deletions(-)

Comments

Sebastian Reichel Dec. 19, 2019, 5:04 p.m. UTC | #1

Hi,

On Thu, Dec 19, 2019 at 04:27:52PM +0200, Claudiu Beznea wrote:
> PMC master clock register offset is different b/w sam9x60 and
> other SoCs. Since there is a need of this register offset in
> shutdown procedure we need to have it per SoC. This is what
> this series does.

Patches look good to me, but I will wait a bit to give Nicolas
and Alexandre a chance to review/test the changes.

-- Sebastian

> Claudiu Beznea (2):
>   power: reset: at91-sama5d2_shdwc: introduce struct shdwc_reg_config
>   power: reset: at91-sama5d2_shdwc: use proper master clock register
>     offset
> 
>  drivers/power/reset/at91-sama5d2_shdwc.c | 75 +++++++++++++++++++++-----------
>  1 file changed, 49 insertions(+), 26 deletions(-)
> 
> -- 
> 2.7.4
>