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X-Microsoft-Antispam-Message-Info: ko4X6I1e7/wyVEJ5G8njboCQRBwnSnDJq33vVSQ2UawEnDKVlC+mzN1+x+uKEb1FVfDKx1EVeL38duEEXWsOP0X06enhnrTPaN/zd/bGPyVFmWagh9YFbR9rzBgsCq7quEE92kwx0daaPJF6p2TCwMZRbxLjcFZiHbJN3jPTyM9q9uy3iz80iAT41u7zIe/mLuDWUtlFcOtfvgCbyLteptQp8EiIf67MuEjLTvvVJFNYVcIrsXp9tUXyCSFS055kBxDTamgOYzf2GGrpeMgo7EVYZ4MXQp4Muk7TCRLChwTr1P/gnthnLxUKHHcbWrldRq8wIBZY/OmAxEZVkorAsQQay8Cm8tkgBUfa7ldGH9PJIyZS9bgRXiz4Yt5K2YDGTquZlzQtNl6b17Y+ZW2BFfHGopHhSXrIQAXSXuhRCkrQDvZ+K+WdGG2yF5EAbtXQo6Ri/abB9MY0Yx1Ifi8PH29pZsyaK9/DkE0qVBDCLldxx6r+sQq572I+wUx395W2i3FofyKpkGdObEF3QMINYw== X-MS-Exchange-AntiSpam-MessageData: zyzREH5ALsEHE7vGFoDL+3FlPHD4Xttcybn6y3fMhJJY76LHHjHOgWnt7dQGbpbKWZVvwzAiaMP0fDX9p3lbOG6X3L7LAMJc4iyviOIvYdkK1ROY9rJ2gMnCBhW51mmyyJbgk+zCqY2OKgVMAx4scg== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7a7531ae-7f73-4deb-7c05-08d7c664e3da X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2020 09:08:12.0089 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: yr4TFWN5N8rSTPnIUoNO0/zHQx2kcRsvjJStYA+i3AQvUUmivM2RCjIaXat0H/fTns4cblpESsknjg1aNnmXrQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB5795 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200312_020817_490963_A8C8D79C X-CRM114-Status: GOOD ( 10.22 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.3 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [40.107.22.65 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid 0.0 MSGID_FROM_MTA_HEADER Message-Id was added by a relay X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peng Fan , fugang.duan@nxp.com, ping.bai@nxp.com, Anson.Huang@nxp.com, andrew.smirnov@gmail.com, daniel.baluta@nxp.com, agx@sigxcpu.org, angus@akkea.ca, heiko@sntech.de, linux-kernel@vger.kernel.org, linux-imx@nxp.com, kernel@pengutronix.de, aford173@gmail.com, l.stach@pengutronix.de, festevam@gmail.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jun.li@nxp.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Peng Fan Patches based on for-next Patch 1,2 is to fix the lockdep warning reported by Leonard Patch 3 is to fix pll mux bit Patch 4 is align with other i.MX8M using gate Patch 5 is to simplify i.MX8MP clk root using composite Patch 3~5 is actually https://patchwork.kernel.org/patch/11402761/ with a minimal change to patch 5 here. Patch 6 is to use composite core clk for A53 clk root Patch 7,8,9 is actually to fix CORE/BUS clk slice issue. This issue is triggerred after we update U-Boot to include the A53 clk fixes to sources from PLL, not from A53 root clk, because of the signoff timing is 1GHz. U-Boot set the A53 root mux to 2, sys pll2 500MHz. Kernel will set the A53 root mux to 4, sys pll1 800MHz, then gate off sys pll2 500MHz. Then kernel will gate off A53 root because clk_ignore_unsed, A53 directly sources PLL, so it is ok to gate off A53 root. However when gate off A53 root clk, system hang, because the original mux sys pll2 500MHz gated off with CLK_OPS_PARENT_ENABLE flag. It is lucky that we not met issue for other core/bus clk slice except A53 ROOT core slice. But it is always triggerred after U-Boot and Linux both switch to use ARM PLL for A53 core, but have different mux settings for A53 root clk slice. So the three patches is to address this issue. Not expect this merge in 5.6 release. Since this patchset is worked out based on for-next and for-next will have conflicts if the patchset based on master. And to make things easier, we let all core/bus use composite api. Patch 10 is make memrepair as critical. Peng Fan (10): arm64: dts: imx8m: assign clocks for A53 clk: imx8m: drop clk_hw_set_parent for A53 clk: imx: imx8mp: fix pll mux bit clk: imx8mp: Define gates for pll1/2 fixed dividers clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code clk: imx8m: migrate A53 clk root to use composite core clk: imx: add mux ops for i.MX8M composite clk clk: imx: add imx8m_clk_hw_composite_bus clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice clk: imx8mp: mark memrepair clock as critical arch/arm64/boot/dts/freescale/imx8mm.dtsi | 10 +- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 10 +- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 11 ++- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 9 +- drivers/clk/imx/clk-composite-8m.c | 74 ++++++++++++++- drivers/clk/imx/clk-imx8mm.c | 27 +++--- drivers/clk/imx/clk-imx8mn.c | 25 +++-- drivers/clk/imx/clk-imx8mp.c | 150 +++++++++++++++--------------- drivers/clk/imx/clk-imx8mq.c | 29 +++--- drivers/clk/imx/clk.h | 7 ++ include/dt-bindings/clock/imx8mp-clock.h | 28 +++++- 11 files changed, 247 insertions(+), 133 deletions(-)