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d="scan'208";a="82772018" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Jul 2020 00:38:33 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Wed, 22 Jul 2020 00:38:33 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Wed, 22 Jul 2020 00:38:29 -0700 From: Claudiu Beznea To: , , , , Subject: [PATCH v2 00/18] clk: at91: add sama7g5 clock support Date: Wed, 22 Jul 2020 10:38:08 +0300 Message-ID: <1595403506-8209-1-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200722_033836_704864_64A05E51 X-CRM114-Status: GOOD ( 12.87 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [68.232.149.84 listed in wl.mailspike.net] -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.149.84 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Claudiu Beznea , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, bbrezillon@kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Hi, This series adds clock support for SAMA7G5. The first patches in series, patches 1/19-9/19, contains some fixes (let me know if you want to send them as a separate series). For SAMA7G5 clock support some AT91 clock drivers needed changes because: 1/ some of generated, master and peripheral clocks could have changeable parents (being able to request frequency changes from parent) 2/ generated and programmable clocks parents needed a mux table as the hardware parent index doesn't correspond with software parent index 3/ there are 4 new master clocks, MCK1..4 (compared with previous AT91 architectures) which are controlled separately from MCK0 4/ some of the PLLs have 2 outputs the internal block schema being as follows: +------+ +--------+ | FRAC |-----+----->| DIVPMC |---> +------+ | +--------+ | | +--------+ +----->| DIVIO |---> +--------+ For this, the clk-sam9x60-pll driver has been re-factored. Changes in v2: - collected Reviewed-by tags - squashed patches 4/19 and 7/19 from previous version - fixed typos in commit description of patch 6/19 from previous version - improve commit description on patch "clk: at91: sckc: register slow_rc with accuracy option" - improve a bit commit description on patch "clk: at91: replace conditional operator with double logical not" - use u64 type for fcore variable in "clk: at91: sam9x60-pll: check fcore against ranges" Claudiu Beznea (18): clk: at91: clk-generated: continue if __clk_determine_rate() returns error clk: at91: clk-generated: check best_rate against ranges clk: at91: clk-sam9x60-pll: fix mul mask clk: at91: sam9x60-pll: use logical or for range check clk: at91: sam9x60-pll: check fcore against ranges clk: at91: sam9x60-pll: use frac when setting frequency clk: at91: sam9x60: fix main rc oscillator frequency clk: at91: sckc: register slow_rc with accuracy option clk: at91: replace conditional operator with double logical not clk: at91: clk-generated: pass the id of changeable parent at registration clk: at91: clk-generated: add mux_table option clk: at91: clk-master: add master clock support for SAMA7G5 clk: at91: clk-peripheral: add support for changeable parent rate clk: at91: clk-programmable: add mux_table option clk: at91: add macro for pll ids mask clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs clk: at91: clk-utmi: add utmi support for sama7g5 clk: at91: sama7g5: add clock support for sama7g5 drivers/clk/at91/Makefile | 1 + drivers/clk/at91/at91rm9200.c | 3 +- drivers/clk/at91/at91sam9260.c | 3 +- drivers/clk/at91/at91sam9g45.c | 3 +- drivers/clk/at91/at91sam9n12.c | 5 +- drivers/clk/at91/at91sam9rl.c | 3 +- drivers/clk/at91/at91sam9x5.c | 7 +- drivers/clk/at91/clk-generated.c | 44 +- drivers/clk/at91/clk-main.c | 6 +- drivers/clk/at91/clk-master.c | 310 +++++++++- drivers/clk/at91/clk-peripheral.c | 111 +++- drivers/clk/at91/clk-programmable.c | 11 +- drivers/clk/at91/clk-sam9x60-pll.c | 547 ++++++++++++------ drivers/clk/at91/clk-system.c | 4 +- drivers/clk/at91/clk-utmi.c | 103 +++- drivers/clk/at91/dt-compat.c | 25 +- drivers/clk/at91/pmc.h | 43 +- drivers/clk/at91/sam9x60.c | 64 ++- drivers/clk/at91/sama5d2.c | 41 +- drivers/clk/at91/sama5d3.c | 6 +- drivers/clk/at91/sama5d4.c | 7 +- drivers/clk/at91/sama7g5.c | 1059 +++++++++++++++++++++++++++++++++++ drivers/clk/at91/sckc.c | 5 +- include/linux/clk/at91_pmc.h | 4 + 24 files changed, 2140 insertions(+), 275 deletions(-) create mode 100644 drivers/clk/at91/sama7g5.c