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X-UUID: 08ac7ae3dd524cb28c862089b44eb01e-20201108 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1170792525; Sun, 08 Nov 2020 18:13:58 -0800 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 8 Nov 2020 18:13:37 -0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 9 Nov 2020 10:13:37 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 9 Nov 2020 10:13:30 +0800 From: Weiyi Lu To: Matthias Brugger , Stephen Boyd , Nicolas Boichat Subject: [PATCH v2 00/13] Clean up the pll_en_bit from en_mask on all the MediaTek clock drivers Date: Mon, 9 Nov 2020 10:13:15 +0800 Message-ID: <1604888008-30555-1-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201108_211402_388797_7B7B627B X-CRM114-Status: GOOD ( 11.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Weiyi Lu , srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series is based on v5.10-rc1 and [v5,07/24] clk: mediatek: Fix asymmetrical PLL enable and disable control[1] in Mediatek MT8192 clock support series [1] https://patchwork.kernel.org/project/linux-mediatek/patch/1604887429-29445-8-git-send-email-weiyi.lu@mediatek.com/ change since v1: - add patch for MT8167 Weiyi Lu (13): clk: mediatek: Clean up the pll_en_bit from en_mask on MT2701 clk: mediatek: Clean up the pll_en_bit from en_mask on MT2712 clk: mediatek: Clean up the pll_en_bit from en_mask on MT6765 clk: mediatek: Clean up the pll_en_bit from en_mask on MT6779 clk: mediatek: Clean up the pll_en_bit from en_mask on MT6797 clk: mediatek: Clean up the pll_en_bit from en_mask on MT7622 clk: mediatek: Clean up the pll_en_bit from en_mask on MT7629 clk: mediatek: Clean up the pll_en_bit from en_mask on MT8135 clk: mediatek: Clean up the pll_en_bit from en_mask on MT8167 clk: mediatek: Clean up the pll_en_bit from en_mask on MT8173 clk: mediatek: Clean up the pll_en_bit from en_mask on MT8183 clk: mediatek: Clean up the pll_en_bit from en_mask on MT8516 clk: mediatek: use en_mask as a pure div_en_mask drivers/clk/mediatek/clk-mt2701.c | 26 +++++++++++++------------- drivers/clk/mediatek/clk-mt2712.c | 30 +++++++++++++++--------------- drivers/clk/mediatek/clk-mt6765.c | 20 ++++++++++---------- drivers/clk/mediatek/clk-mt6779.c | 24 ++++++++++++------------ drivers/clk/mediatek/clk-mt6797.c | 20 ++++++++++---------- drivers/clk/mediatek/clk-mt7622.c | 18 +++++++++--------- drivers/clk/mediatek/clk-mt7629.c | 12 ++++++------ drivers/clk/mediatek/clk-mt8135.c | 20 ++++++++++---------- drivers/clk/mediatek/clk-mt8167.c | 16 ++++++++-------- drivers/clk/mediatek/clk-mt8173.c | 28 ++++++++++++++-------------- drivers/clk/mediatek/clk-mt8183.c | 22 +++++++++++----------- drivers/clk/mediatek/clk-mt8516.c | 12 ++++++------ drivers/clk/mediatek/clk-pll.c | 12 ++++-------- 13 files changed, 128 insertions(+), 132 deletions(-)