From patchwork Tue Dec 22 13:09:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 11986513 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA652C433DB for ; Tue, 22 Dec 2020 13:12:18 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 636F42312E for ; Tue, 22 Dec 2020 13:12:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 636F42312E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=iv+Ngd6A6TsiHOHwxFoK/L/YdUoPF246Wv39J38t4O4=; b=e8CwOIm4HtqZ9yjBxYhZhGeIO5 gkDHz+J7gNFo/kPlPCRxnieHq/cuNK7Jij8ad9ZfjdLTTtmwzp3PWVWCSyQxXW/br2iQmiwON2oKy zMNRYumfhl6RG5Sv55jrZOkGJO1nNPW7Mq2/3z222ZdUamB7Nu8moA9xEKf64E7HKNhJpESJJqWsF 8XaSmiWj3YLO+yhJHUJG1ymMDXJFyQ0tRiq1ERAHtbz8jZSWonmRFpMDJSE+jUk7EcaWdfIVAe3B6 gBfMt/D1gtVC1A8z2bqtsYFkU3rmM0AFEr5VGGiAv43vtuXlZ406zBOTfLw5V3mQzg0ZfqRex47GV q4frd49A==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1krhQx-0001tP-5o; Tue, 22 Dec 2020 13:10:35 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1krhQh-0001mW-5u; Tue, 22 Dec 2020 13:10:20 +0000 X-UUID: eb19003ce70e4367bccee927d63a9495-20201222 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=aLXcjLlIyzrYGYS5S2udIfReEWFIL3dxvYtsBPmZI2g=; b=lXLCYIcgFg/V24E8FNlXYnJ3x01Ex7i+yb3aAt7DTU7t3IcQMWfDVxpgTsyeo79c0mXshooqcBBcXwTMRy7rA2dDjLiFSJ1Br6UurS9jwd++OCsqzsJtuQNs+lf5Iw2WVgMz1AW4fofiGX6Jnx/0K77lrdSIXD2/iURIvUePcqs=; X-UUID: eb19003ce70e4367bccee927d63a9495-20201222 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1751204055; Tue, 22 Dec 2020 05:10:02 -0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 22 Dec 2020 05:09:51 -0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 22 Dec 2020 21:09:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 22 Dec 2020 21:09:48 +0800 From: Weiyi Lu To: Matthias Brugger , Rob Herring , Stephen Boyd , Nicolas Boichat Subject: [PATCH v6 00/22] Mediatek MT8192 clock support Date: Tue, 22 Dec 2020 21:09:25 +0800 Message-ID: <1608642587-15634-1-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201222_081019_492334_273800A4 X-CRM114-Status: GOOD ( 13.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Weiyi Lu , srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, Project_Global_Chrome_Upstream_Group@mediatek.com, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series is based on v5.10-rc1. change since v5: - remove unused clocks by rolling Tinghan's patches[1][2] into series [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=398781 [2] https://patchwork.kernel.org/project/linux-mediatek/list/?series=405143 - remove dts related patches from series change since v4: - merge some subsystem into same driver - add a generic probe function to reduce duplicated code changes since v3: - add critical clocks - split large patches into small ones changes since v2: - update and split dt-binding documents by functionalities - add error checking in probe() function - fix incorrect clock relation and add critical clocks - update license identifier and minor fix of coding style changes since v1: - fix asymmetrical control of PLL - have en_mask used as divider enable mask on all MediaTek SoC Weiyi Lu (22): dt-bindings: ARM: Mediatek: Add new document bindings of imp i2c wrapper controller dt-bindings: ARM: Mediatek: Add new document bindings of mdpsys controller dt-bindings: ARM: Mediatek: Add new document bindings of msdc controller dt-bindings: ARM: Mediatek: Add new document bindings of scp adsp controller dt-bindings: ARM: Mediatek: Document bindings of MT8192 clock controllers clk: mediatek: Add dt-bindings of MT8192 clocks clk: mediatek: Fix asymmetrical PLL enable and disable control clk: mediatek: Add configurable enable control to mtk_pll_data clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers clk: mediatek: Add MT8192 basic clocks support clk: mediatek: Add MT8192 audio clock support clk: mediatek: Add MT8192 camsys clock support clk: mediatek: Add MT8192 imgsys clock support clk: mediatek: Add MT8192 imp i2c wrapper clock support clk: mediatek: Add MT8192 ipesys clock support clk: mediatek: Add MT8192 mdpsys clock support clk: mediatek: Add MT8192 mfgcfg clock support clk: mediatek: Add MT8192 mmsys clock support clk: mediatek: Add MT8192 msdc clock support clk: mediatek: Add MT8192 scp adsp clock support clk: mediatek: Add MT8192 vdecsys clock support clk: mediatek: Add MT8192 vencsys clock support .../arm/mediatek/mediatek,apmixedsys.txt | 1 + .../bindings/arm/mediatek/mediatek,audsys.txt | 1 + .../bindings/arm/mediatek/mediatek,camsys.txt | 22 + .../bindings/arm/mediatek/mediatek,imgsys.txt | 2 + .../arm/mediatek/mediatek,imp_iic_wrap.yaml | 78 + .../arm/mediatek/mediatek,infracfg.txt | 1 + .../bindings/arm/mediatek/mediatek,ipesys.txt | 1 + .../arm/mediatek/mediatek,mdpsys.yaml | 38 + .../bindings/arm/mediatek/mediatek,mfgcfg.txt | 1 + .../bindings/arm/mediatek/mediatek,mmsys.txt | 1 + .../bindings/arm/mediatek/mediatek,msdc.yaml | 46 + .../arm/mediatek/mediatek,pericfg.yaml | 1 + .../arm/mediatek/mediatek,scp-adsp.yaml | 38 + .../arm/mediatek/mediatek,topckgen.txt | 1 + .../arm/mediatek/mediatek,vdecsys.txt | 8 + .../arm/mediatek/mediatek,vencsys.txt | 1 + drivers/clk/mediatek/Kconfig | 80 + drivers/clk/mediatek/Makefile | 13 + drivers/clk/mediatek/clk-mt8192-aud.c | 118 ++ drivers/clk/mediatek/clk-mt8192-cam.c | 107 ++ drivers/clk/mediatek/clk-mt8192-img.c | 70 + .../clk/mediatek/clk-mt8192-imp_iic_wrap.c | 119 ++ drivers/clk/mediatek/clk-mt8192-ipe.c | 57 + drivers/clk/mediatek/clk-mt8192-mdp.c | 82 + drivers/clk/mediatek/clk-mt8192-mfg.c | 50 + drivers/clk/mediatek/clk-mt8192-mm.c | 108 ++ drivers/clk/mediatek/clk-mt8192-msdc.c | 85 ++ drivers/clk/mediatek/clk-mt8192-scp_adsp.c | 50 + drivers/clk/mediatek/clk-mt8192-vdec.c | 94 ++ drivers/clk/mediatek/clk-mt8192-venc.c | 53 + drivers/clk/mediatek/clk-mt8192.c | 1326 +++++++++++++++++ drivers/clk/mediatek/clk-mtk.c | 23 + drivers/clk/mediatek/clk-mtk.h | 10 + drivers/clk/mediatek/clk-mux.h | 15 + drivers/clk/mediatek/clk-pll.c | 31 +- include/dt-bindings/clock/mt8192-clk.h | 585 ++++++++ 36 files changed, 3310 insertions(+), 7 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,imp_iic_wrap.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mdpsys.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,msdc.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,scp-adsp.yaml create mode 100644 drivers/clk/mediatek/clk-mt8192-aud.c create mode 100644 drivers/clk/mediatek/clk-mt8192-cam.c create mode 100644 drivers/clk/mediatek/clk-mt8192-img.c create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c create mode 100644 drivers/clk/mediatek/clk-mt8192-ipe.c create mode 100644 drivers/clk/mediatek/clk-mt8192-mdp.c create mode 100644 drivers/clk/mediatek/clk-mt8192-mfg.c create mode 100644 drivers/clk/mediatek/clk-mt8192-mm.c create mode 100644 drivers/clk/mediatek/clk-mt8192-msdc.c create mode 100644 drivers/clk/mediatek/clk-mt8192-scp_adsp.c create mode 100644 drivers/clk/mediatek/clk-mt8192-vdec.c create mode 100644 drivers/clk/mediatek/clk-mt8192-venc.c create mode 100644 drivers/clk/mediatek/clk-mt8192.c create mode 100644 include/dt-bindings/clock/mt8192-clk.h Reviewed-by: James Liao