From patchwork Mon Feb 8 07:20:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shaokun Zhang X-Patchwork-Id: 12074115 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F2C7C433DB for ; Mon, 8 Feb 2021 07:22:56 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 21D3364E22 for ; Mon, 8 Feb 2021 07:22:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 21D3364E22 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=hisilicon.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=2KgaDJP3g83bgsE/M+6JojzAtorbBBMuzfv3G5C58OU=; b=wD497jptYmuWhTlncqpQVfi6vO I23Qrj0/0sYY9yag8fDJZ95nttowggZBPbaHgpi2fBH9MjZ0vTbTk22JOcW0A9H3w38QHHkyurQ3V +UJmoJe7t3U2uEI0oPxqtx7STpzz5QXMjmWM7IuvU10gp7ndBWWhn/EZ3ni2U5RPhWf1gYqulNgJu Me6WAvqt+97y0SvJSCWgWlzi2KPatnvsmoHpQVvlQN8imCT6uiD5HLXUpWH0sjw1usVL06q7IhdVB IFJwKB1ozGBHQysckFenUP3sOTpGEQ0py4X47VOrXtEK0cUa3CXx03/OKzu1LTTDH5AFnWyQnJoT2 wcj8Vo3g==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l90rN-0002di-PU; Mon, 08 Feb 2021 07:21:25 +0000 Received: from szxga06-in.huawei.com ([45.249.212.32]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l90rJ-0002bM-1n for linux-arm-kernel@lists.infradead.org; Mon, 08 Feb 2021 07:21:22 +0000 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4DYy8c2g1GzjK8r; Mon, 8 Feb 2021 15:20:00 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.498.0; Mon, 8 Feb 2021 15:20:58 +0800 From: Shaokun Zhang To: Subject: [PATCH v3 0/9] Add support for HiSilicon Hip09 uncore PMU driver Date: Mon, 8 Feb 2021 15:20:23 +0800 Message-ID: <1612768832-23733-1-git-send-email-zhangshaokun@hisilicon.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210208_022121_366108_83EC3AC7 X-CRM114-Status: GOOD ( 11.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Qi Liu , John Garry , Shaokun Zhang , Jonathan Cameron , Will Deacon Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patchset adds support for HiSilicon Hip09 SoC uncore PMUs driver which is PMU v2 and it includes: (a) Cleanup the unnecessary sanity check in patch1; (b) Refactor interrupt registration and handler function for later new uncore PMU driver in patch2; (c) Update the PMU version suffiex for existing driver in patch3 (d) Some new functions are added on L3C/HHA PMU in patch4/5; (e) New DDRC PMU model is supported using programable counter and supports more events in patch6; (f) Add new modules SLLC and PA PMU drivers in patch7/8; (g) Update the perf document for the new functions and modules in patch9; ChangeLog v2-->v3: 1. Address Mark's comments adding detailed description in git commit log to introduce new filters 2. Fix some typos 3. Add one cleanup patch to remove redundant check v1-->v2: 1. Address John's comments and fix some typos 2. Add John's Reviewed-by tags Cc: Mark Rutland Cc: Will Deacon Cc: John Garry Cc: Jonathan Cameron Cc: Qi Liu Shaokun Zhang (9): drivers/perf: hisi: Remove unnecessary check of counter index drivers/perf: hisi: Refactor code for more uncore PMUs drivers/perf: hisi: Add PMU version for uncore PMU drivers. drivers/perf: hisi: Add new functions for L3C PMU drivers/perf: hisi: Add new functions for HHA PMU drivers/perf: hisi: Update DDRC PMU for programable counter drivers/perf: hisi: Add support for HiSilicon SLLC PMU driver drivers/perf: hisi: Add support for HiSilicon PA PMU driver docs: perf: Add new description on HiSilicon uncore PMU v2 Documentation/admin-guide/perf/hisi-pmu.rst | 49 +++ drivers/perf/hisilicon/Makefile | 3 +- drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c | 348 +++++++++++------ drivers/perf/hisilicon/hisi_uncore_hha_pmu.c | 301 ++++++++++----- drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 355 ++++++++++++----- drivers/perf/hisilicon/hisi_uncore_pa_pmu.c | 500 ++++++++++++++++++++++++ drivers/perf/hisilicon/hisi_uncore_pmu.c | 71 +++- drivers/perf/hisilicon/hisi_uncore_pmu.h | 20 +- drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c | 530 ++++++++++++++++++++++++++ include/linux/cpuhotplug.h | 2 + 10 files changed, 1864 insertions(+), 315 deletions(-) create mode 100644 drivers/perf/hisilicon/hisi_uncore_pa_pmu.c create mode 100644 drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c