From patchwork Mon Oct 29 07:25:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 10658807 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0F056109C for ; Mon, 29 Oct 2018 07:28:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EB1E5294C1 for ; Mon, 29 Oct 2018 07:28:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D8F4429620; Mon, 29 Oct 2018 07:28:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9636E294C1 for ; Mon, 29 Oct 2018 07:28:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=4DBbfOJACnhgAN09ExOY537A9kXIH9Sis+uoBqze1EE=; b=ueV6p3IXt/W/Ln M7kt/+XLclyGET8pFIJ/Fdev4le1u3vUaLP6y+/S1O1uhJVOUdKz3IX5V81bK8zn7elPVfipP7mWc bcVum9875x75ur7YLHZguk5dB9byGT6WJh+300HGaKoA8qw2+rlU1MTGMQqKvdSpNbrdtcx4H909I VddQeWd62cakctajjLEVal59RssL97gLM5UvWFB0DV+BbTh7yl0Fbhx20dwO9t+/Dr6v1EtYb7KX0 iSUfcrKhuDTnW65SmdoT9Yi82B9FdDbPdqRH+6o6CeD7zW80gKo9j/FlUdSJ6OQHnFiy/CbQz+VXV AE/jcyAvS2FnwWRn0bvg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gH1yP-0001B6-7d; Mon, 29 Oct 2018 07:28:29 +0000 Received: from gate2.alliedtelesis.co.nz ([2001:df5:b000:5::4]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gH1wH-0000Ck-TN for linux-arm-kernel@lists.infradead.org; Mon, 29 Oct 2018 07:26:22 +0000 Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 80DE38364E; Mon, 29 Oct 2018 20:25:53 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1540797953; bh=KDacA1qLqffnghFCdx82scWoqUVQ1YlKQBJgT2xXNLA=; h=From:To:Cc:Subject:Date; b=t5CstN0B7qlxNEs09rM9U+vtZK6LCon7I2FHRvyCsvGwmF+n0E5gkXq5vHYv5K2Lu bVkpYNsS4oYHAGPF74EEIe1o+Raoj1zH0Ov1CQvEXLlNkskYGKnjc01c5FKbuaNWRH vMq/zSGcHnJAcZwr/vEtAikPdWZNLTB1mWn1RmLJwhKINEDlprsY9p4GjmBlXMNjcr 2FJD9NBbTqyCxKNpLf5eqmLlD9x19jQfLnyLR89pDRfRipuJehMSAuOC6tYzHbyyQ4 IOlsXPSlTEyfnwkSBr50NR7G3D1WhGMoEtD2v9SoIFFCjwEEKkwwibOLay39RBXCNO NUGddi8DIHEuA== Received: from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 29 Oct 2018 20:25:53 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by smtp (Postfix) with ESMTP id 1442613EF06; Mon, 29 Oct 2018 20:25:53 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 3797E1E21FF; Mon, 29 Oct 2018 20:25:48 +1300 (NZDT) From: Chris Packham To: linux@armlinux.org.uk Subject: [PATCH v5 0/8] EDAC drivers for Armada XP L2 and DDR Date: Mon, 29 Oct 2018 20:25:27 +1300 Message-Id: <20181029072535.31667-1-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 x-atlnz-ls: pat X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181029_002618_428315_9D03A8F3 X-CRM114-Status: GOOD ( 13.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jlu@pengutronix.de, linux-kernel@vger.kernel.org, Chris Packham , bp@alien8.de, u.kleine-koenig@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The current plan is for these to go in via the ARM tree once appropriate Reviews/Acks have been given. This series adds drivers for the L2 cache and DDR RAM ECC functionality as found on the MV78230/MV78x60 SoCs. Jan has tested these changes with the MV78460 (on a custom board with a DDR3 ECC DIMM), Chris has tested these changes with 88F6820 and 98dx3236 (both a custom boards with fixed DDR3 + ECC). Also contained in this series is an additional debugfs wrapper. Compared to the previous v4 series I've added my s-o-b to some of Jan's patches and rebased against v4.19.0. Compared to the previous v3 series, the following changes have been made: - Use shorter names for the AURORA ECC and parity registers - Numerous formatting changes to edac/armada_xp.c (as requested by Boris) - Added support for Armada-38x and 98dx3236 SoCs Compared to the previous v2 series, the following changes have been made: - Allocate EDAC structures later during probing and drop devres support patches (requested by Boris) - Make drvdata->width usage consistent according to the comment (suggested by Chris) Compared to the previous v1 series, the following changes have been made: - Add the aurora-l2 register defines earlier in the series (suggested by Russell King and Gregory CLEMENT ) - Changed the DT vendor prefix from "arm" to "marvell" for the ecc-enable/disable properties on the aurora-l2 (suggested by Russell King) - Fix some warnings reported by checkpatch Compared to the original RFC series, the following changes have been made: - Integrated Chris' patches for parity and ECC configuration via DT - Merged the DDR RAM and L2 cache drivers (as requested by Boris, analogous to fsl_ddr_edac.c and mpc85xx_edac.c) - Added myself to MAINTAINERS (requested by Boris) - L2 cache: Track the msg size and use snprintf (review comment by Chris) - L2 cache: Split error injection from the check function (review comment by Chris) - DDR RAM: Allow 16 bit width in addition to 32 and 64 bit (review comment by Chris) - Use of_match_ptr() (review comments by Chris) - Minor checkpatch cleanups Chris Packham (3): ARM: l2x0: support parity-enable/disable on aurora ARM: l2x0: add marvell,ecc-enable property for aurora EDAC: armada_xp: Add support for more SoCs Jan Luebbe (5): ARM: l2c: move cache-aurora-l2.h to asm/hardware ARM: aurora-l2: add prefix to MAX_RANGE_SIZE ARM: aurora-l2: add defines for parity and ECC registers EDAC: Add missing debugfs_create_x32 wrapper EDAC: Add driver for the Marvell Armada XP SDRAM and L2 cache ECC .../devicetree/bindings/arm/l2c2x0.txt | 2 + MAINTAINERS | 6 + .../asm/hardware}/cache-aurora-l2.h | 50 +- arch/arm/mm/cache-l2x0.c | 20 +- drivers/edac/Kconfig | 7 + drivers/edac/Makefile | 1 + drivers/edac/armada_xp_edac.c | 644 ++++++++++++++++++ drivers/edac/debugfs.c | 11 + drivers/edac/edac_module.h | 5 + 9 files changed, 742 insertions(+), 4 deletions(-) rename arch/arm/{mm => include/asm/hardware}/cache-aurora-l2.h (50%) create mode 100644 drivers/edac/armada_xp_edac.c