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DIR:OUT; SFP:1101; SCL:1; SRVR:SN6PR07MB4863; H:SN6PR07MB5326.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: cavium.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: wmKm/bPYKCNs/7mDPJ+4ZDCPNXh5wp8V0XeGoZ8PBg+NY0oGnyfXH7b7TcIFBtoFdx7ZTL3pp4SMhX/4LuL5YjRqwAmBIJomTvsqVHHWUODV78cRw2OLqreCKxEfrgzn3/JWpKgaVDOtvSjGhZQ7xlEPkmNkVN9TBF0tvKyQxELA8TSZQ9pxMueAl4DaykR+eSisB6Lzd2v7VH4dsJeRDu132EVwF7uRoGsmKjQKNYG8IEH5nn/m1XEc01VALk5n58+47NdI9Sr62xF4HiJtEOBmGMyNfuRvnZBeaKkDf1SGVFKDbWdie8qBRPYNgbH98pkmVOXBUxlWPePeVkSoJPsKByDbP83jMOpCGoiRxyY= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: cavium.com X-MS-Exchange-CrossTenant-Network-Message-Id: cb5415b5-ac0d-4c97-0105-08d64b446c9e X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Nov 2018 21:50:57.7481 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 711e4ccf-2e9b-4bcf-a551-4094005b6194 X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR07MB4863 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181115_135111_959874_CF683CC3 X-CRM114-Status: GOOD ( 11.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lorenzo Pieralisi , Julien Thierry , John Garry , Will Deacon , "linux-kernel@vger.kernel.org" , "Richter, Robert" , Matthias Brugger , "linux-arm-kernel@lists.infradead.org" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The gicv3-its device table may have a size of up to 16MB (Cavium ThunderX). With 4k pagesize the maximum size of memory allocation is 4MB. This series implements the use of CMA for allocation of large its tables. To achieve this we need to make an its node a kernel device (patch #1) and rework the its table allocation code (patch #2). Both can only be done after the arch_initcall and thus this patch series bases on my previous series that implements late its initialization: https://patchwork.kernel.org/cover/10673117/ Using its nodes as kernel devices has the side effect to ease the release of resources (devres used) and device based messages (dev_* printk variants used). The new its table allocator still uses the old scheme for small tables to allow a further rework that supports NUMA-aware its tables. Robert Richter (2): irqchip/gic-v3-its: Handle its nodes as kernel devices irqchip/gic-v3-its: Use CMA for allocation of large device tables drivers/irqchip/irq-gic-v3-its.c | 224 +++++++++++++++++++++++---------------- 1 file changed, 135 insertions(+), 89 deletions(-)