[0/3] Add SPI pinctrl nodes to sun5i SoCs.

Message

Josef Luštický Jan. 23, 2019, 9:43 a.m. UTC

This patch series adds SPI pinctrl nodes to sun5i SoCs.

While spi0 is common to all A10s, A13 and GR8 (PATCH 1/3),
spi2 has alternate pins on the PB bank only on A10s (already in sun5i-a10s.dtsi) and GR8 (PATCH 2/3).

The spi1_cs1 is only available on A10s (PATCH 3/3).

The spi1_cs1 is potentially available on GR8 as well
(at least it is specified in drivers/pinctrl/sunxi/pinctrl-sun5i.c),
but I was not able to find it in the datasheet.
The same applies to spi2_cs1.

Both spi1_cs1 and spi2_cs1 can be added later to sun5i-gr8.dtsi.

Josef Lusticky (3):
  ARM: dts: sun5i: Add SPI0 pins
  ARM: dts: sun5i: GR8: Add SPI2 PB pins
  ARM: dts: sun5i: A10s: Add SPI1_CS1 PG13 pin

 arch/arm/boot/dts/sun5i-a10s.dtsi |  5 +++++
 arch/arm/boot/dts/sun5i-gr8.dtsi  | 10 ++++++++++
 arch/arm/boot/dts/sun5i.dtsi      | 10 ++++++++++
 3 files changed, 25 insertions(+)

Comments

Maxime Ripard Jan. 23, 2019, 10:36 a.m. UTC | #1

Hi Joseph,

On Wed, Jan 23, 2019 at 10:43:31AM +0100, Josef Lusticky wrote:
> This patch series adds SPI pinctrl nodes to sun5i SoCs.
> 
> While spi0 is common to all A10s, A13 and GR8 (PATCH 1/3),
> spi2 has alternate pins on the PB bank only on A10s (already in sun5i-a10s.dtsi) and GR8 (PATCH 2/3).
> 
> The spi1_cs1 is only available on A10s (PATCH 3/3).
> 
> The spi1_cs1 is potentially available on GR8 as well
> (at least it is specified in drivers/pinctrl/sunxi/pinctrl-sun5i.c),
> but I was not able to find it in the datasheet.
> The same applies to spi2_cs1.
> 
> Both spi1_cs1 and spi2_cs1 can be added later to sun5i-gr8.dtsi.

Thanks for your patches, unfortunately, in order to keep the DT size
reasonable, if there's no user of the pinctrl node we don't merge
them. If you have a board that would use it, you can still send those
changes at the same time.

Thanks!
Maxime