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Tue, 5 Feb 2019 00:17:37 +0000 From: Trent Piepho To: "linux-pci@vger.kernel.org" Subject: [PATCH v2 0/3] Workaround for IMX7d PCI-e PLL lock failure Thread-Topic: [PATCH v2 0/3] Workaround for IMX7d PCI-e PLL lock failure Thread-Index: AQHUvOgyHlSpLFtcN0Os+r6exyadWw== Date: Tue, 5 Feb 2019 00:17:37 +0000 Message-ID: <20190205001721.18639-1-tpiepho@impinj.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BYAPR07CA0078.namprd07.prod.outlook.com (2603:10b6:a03:12b::19) To MWHPR0601MB3708.namprd06.prod.outlook.com (2603:10b6:301:7c::38) authentication-results: spf=none (sender IP is ) smtp.mailfrom=tpiepho@impinj.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.14.4 x-originating-ip: [216.207.205.253] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; MWHPR0601MB3722; 6:lv6tWS8WWFckIROI9kNCtkJ/ELc75Jawg748op2DXkUp40i8kLE/yWm2+lPvj1veFp7kZLmMbvHsmpAZ87TcVsgqcGWu95tanlKjE4cpz8wxJ6bTC3ka/RuKBp5dKWphVCRPCUfvBoYVIFdgsKc0MyvtDsXPniWtM4t1BZhnDAxrQ96Oy0fbWYKdR/ivysQz46/Lm4p/lmLuaD81XbY41P0WPlUskwFtppVp/1915U6rT6Ng88PzKcdjJraQ73tbxSxsJw0cFf9cSh18TwxHVfro61sKdsfTm/Fn4Gc6T0yR2oels3p1ta6zE3lFZqIn5bLGbAMe9VOAiWHuT80mhG4OcK6tOXoYy0kzzJKNFIW8aWPLuVYgPyRwOaylLnMbHFuz3/rxG66qBYdUI9oe9L2/NL5UKtZD3WYyRli+yG5Srk1WBIAdzB3TaFliWDSphJrrfWfmhWbD3ZB0IVPjGQ==; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lorenzo Pieralisi , Richard Zhu , Lucas Stach , Shawn Guo , "linux-arm-kernel@lists.infradead.org" , Trent Piepho Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This is the workaround for the IMX7d Erratum e10728, failure of initialize PCIe PLL VCO oscillation resulting in PLL lock failure and failure of the PCI-e link to come up. The registers used in the workaround are based on the latest patch in the NXP kernel. This uses a new node of type fsl,imx7d-pcie-phy to get the PHY's registers. The node is found via a phandle, named fsl,imx7d-pcie-phy, added to the PCI-e controller's node. If the phandle is not present, or otherwise incorrect, there is a warning message on IMX7d. While the PHY's register could be added as another bank in the PCI-e controller's register space, this isn't an accurate description of the hardware. The PHY is a different device and attached to a different AIPS bus. Changes since v1: Renamed imx-pcie-phy to imx7d-pci-phy since it appears this phy is specific to the imx7d. Split out dts binding change into its own patch. Changed error message to warning and improved it. Trent Piepho (3): dt-bindings: imx6q-pcie: Add description of imx7d pcie phy ARM: dts: imx7d: Add node for PCIe PHY PCI: imx: Add workaround for e10728, IMX7d PCIe PLL failure .../devicetree/bindings/pci/fsl,imx6q-pcie.txt | 11 +++++ arch/arm/boot/dts/imx7d.dtsi | 9 ++++ drivers/pci/controller/dwc/pci-imx6.c | 57 ++++++++++++++++++++++ 3 files changed, 77 insertions(+)