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Fri, 19 Apr 2019 10:19:29 -0700 (PDT) From: Bryan O'Donoghue To: l.stach@pengutronix.de, peng.fan@nxp.com, shawnguo@kernel.org, srinivas.kandagatla@linaro.org, leonard.crestez@nxp.com Subject: [PATCH v3 0/5] Add i.MX8MM support Date: Fri, 19 Apr 2019 18:19:22 +0100 Message-Id: <20190419171927.24269-1-pure.logic@nexus-software.ie> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190419_101931_993675_E59E19F0 X-CRM114-Status: GOOD ( 11.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aisheng.dong@nxp.com, abel.vesa@nxp.com, anson.huang@nxp.com, linux-imx@nxp.com, kernel@pengutronix.de, fabio.estevam@nxp.com, Bryan O'Donoghue , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP V3: - Fix commit log for the expanding the ADDR field i.MX6 uses seven not four bits, which is why the existing define says 0x7F not 0x0F - bod V2: - Rebased to linux-next/master to align with i.8MQ work - Two patches dropped as a result of rebase - Added patch to expand OCOTP_CTRL_ADDR to 8 bits for all users - Leonard - Makes sure nregs = 60 not 64 for i.MX8MM - Tested imx8mm-evk, imx7s-warp7 V1: This set adds support for the i.MX8MM. When adding support for this processor there are two interesting gotchas to watch for. #1 We current do not preserve the WAIT field for i.MX6 and since we are reusing the i.MX6 set_timing() values, this would also affect i.MX8. On the face of it, it appears to be an inocuous error with no real side effects. #2 Secondly the i.MX8MM will calculate a zero value for the RELAX bit-field when programming up OTP fuses. This is fine for programming the fuses but, it introduces a strange failure state with reloading the shadow registers subsequent to blowing an OTP fuse. The second important patch here then is ensuring the RELAX field is non-zero to avoid the failure state. Bryan O'Donoghue (5): nvmem: imx-ocotp: Elongate OCOTP_CTRL ADDR field to eight bits nvmem: imx-ocotp: Ensure WAIT bits are preserved when setting timing nvmem: imx-ocotp: Ensure the RELAX field is non-zero nvmem: imx-ocotp: Add i.MX8MM support dt-bindings: imx-ocotp: Add i.MX8MM compatible .../devicetree/bindings/nvmem/imx-ocotp.txt | 1 + drivers/nvmem/imx-ocotp.c | 14 ++++++++++++-- 2 files changed, 13 insertions(+), 2 deletions(-)