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Wed, 29 May 2019 01:21:47 -0700 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter , Rob Herring , Stephen Boyd Subject: [PATCH V4 0/8] Add EMC scaling support for Tegra210 Date: Wed, 29 May 2019 16:21:31 +0800 Message-ID: <20190529082139.5581-1-josephl@nvidia.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1559118108; bh=XuNQ9UxKIn9U28BU9jOdmmgvQosuL6obR6fs0OHQgc8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: MIME-Version:X-NVConfidentiality:Content-Transfer-Encoding: Content-Type; b=JaEUta0hBxrysDVALtbxkUDF7PypdzoO4E65UJm7VcEk1h4OGOm4dGxvxJQzLjSYs 6JpcIBTw6fF5GxdB18KLUlO8T4S1Oa5prIXCa6/wcDNE8wT2gzpPyVRw0ri42VSIHr 8dWPJZjR7qbORlnZw61CnWHHjpri4iI478XlhfseroebGaI8h0sG3JAjeXINwPcg/4 F/VB9aQIEsnh34a6BP7z1o2BmIJUsiWDAK+PR4pT3YGRBBBSrXo8ejx3xf/LEPd8th aihAplo88iuIrbYap9C5cMTwR37imXUyh8wQelM41RebWBNroY2iVLk34j7HQjLYmv bOyHTux0bbMOg== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190529_012150_974555_E783F6D9 X-CRM114-Status: GOOD ( 11.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This series introduces the EMC clock scaling support for Tegra210. The new version has a significant change, which drops the EMC table bindings and replaces by memory region node of EMC table. And most of the comments in V1 have been addressed. Thanks. v4: * make sure the behavior is compatible with the case if the kernel uses the older DTB which doesn't have EMC node. * remove the EMC clock statistic data in EMC debug fs. Joseph Lo (8): dt-bindings: memory: tegra: Add external memory controller binding for Tegra210 clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210 clk: tegra: Export functions for EMC clock scaling memory: tegra: Add Tegra210 EMC clock driver memory: tegra: Add EMC scaling support code for Tegra210 memory: tegra: Add EMC scaling sequence code for Tegra210 clk: tegra: Remove the old emc_mux clock for Tegra210 arm64: tegra: Add external memory controller node for Tegra210 .../nvidia,tegra210-emc.txt | 55 + arch/arm64/boot/dts/nvidia/tegra210.dtsi | 33 + drivers/clk/tegra/clk-tegra210.c | 89 +- drivers/memory/tegra/Kconfig | 10 + drivers/memory/tegra/Makefile | 1 + drivers/memory/tegra/tegra210-emc-cc-r21021.c | 1953 ++++++++++++++++ drivers/memory/tegra/tegra210-emc.c | 2041 +++++++++++++++++ drivers/memory/tegra/tegra210-emc.h | 1031 +++++++++ include/dt-bindings/clock/tegra210-car.h | 4 +- include/linux/clk/tegra.h | 5 + include/soc/tegra/emc.h | 2 + 11 files changed, 5207 insertions(+), 17 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt create mode 100644 drivers/memory/tegra/tegra210-emc-cc-r21021.c create mode 100644 drivers/memory/tegra/tegra210-emc.c create mode 100644 drivers/memory/tegra/tegra210-emc.h