From patchwork Tue Jun 11 14:09:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 10987033 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EB38376 for ; Tue, 11 Jun 2019 14:11:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D9DFB2842E for ; Tue, 11 Jun 2019 14:11:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CD5B0283C5; Tue, 11 Jun 2019 14:11:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 631D6283C5 for ; Tue, 11 Jun 2019 14:11:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=a/3D4nBCenjwfNauht4670bJHsrJhGwgEHDYZsYyNF0=; b=AllcIp7ETN7YJl aMDq1b7z+jqIZjaiG5/V4jpDbxpim8RZbvGYGisiIus8UhYmxf5UZxW8600toyapRS6kGpLq81Pu1 wG3Eck+1CpGl+hQEGJsbmhoQBMfiKVBeBaz4yOUjAOmykqYGfSAOGEXl+ifrxxgwknVo3HFutDdoH ZSz/pUvOmG91LmJKG+M2Bakl809gTTlEdOCAyYyBnT6jzb+E5U6NvmwPluSdmaorUyxQETff7Mm0I LGyZRY+EJLMEXEx9Ptq2Y8NTUm6ZDqWPG4Bzn2liQBDHAKnuYZv5OTJHA08T9UXYKw8EkM6K1FBRM 0KU+iloDLLx34BNjHPxA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hahUJ-0002yY-0m; Tue, 11 Jun 2019 14:10:59 +0000 Received: from haggis.mythic-beasts.com ([2a00:1098:0:86:1000:0:2:1]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hahUF-0002xF-9u for linux-arm-kernel@lists.infradead.org; Tue, 11 Jun 2019 14:10:57 +0000 Received: from [199.195.250.187] (port=52613 helo=hermes.aosc.io) by haggis.mythic-beasts.com with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1hahU6-0002bJ-Ao; Tue, 11 Jun 2019 15:10:46 +0100 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id E9C69819F0; Tue, 11 Jun 2019 14:10:35 +0000 (UTC) From: Icenowy Zheng To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Linus Walleij Subject: [PATCH v2 00/11] Support for Allwinner V3/S3L and Sochip S3 Date: Tue, 11 Jun 2019 22:09:29 +0800 Message-Id: <20190611140940.14357-1-icenowy@aosc.io> MIME-Version: 1.0 X-BlackCat-Spam-Score: 24 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190611_071055_343386_73AAEC9E X-CRM114-Status: GOOD ( 15.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Icenowy Zheng Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patchset tries to add support for Allwinner V3/S3L and Sochip S3. Allwinner V3/V3s/S3L and Sochip S3 share the same die, but with different package. V3 is BGA w/o co-packaged DDR, V3s is QFP w/ DDR2, S3L is BGA w/ DDR2 and S3 is BGA w/ DDR3. (S3 and S3L is compatible for pinout, but because of different DDR, DDR voltage is different between the two variants). Because of the pin count of V3s is restricted due to the package, some pins are not bound on V3s, but they're bound on V3/S3/S3L. Currently the kernel is only prepared for the features available on V3s. This patchset adds the features missing on V3s for using them on V3/S3/S3L, and add bindings for V3/S3/S3L. It also adds a S3 SoM by Sipeed, called Lichee Zero Plus. Icenowy Zheng (11): dt-bindings: pinctrl: add missing compatible string for V3s dt-bindings: pinctrl: add compatible string for Allwinner V3 pinctrl pinctrl: sunxi: v3s: introduce support for V3 clk: sunxi-ng: v3s: add the missing PLL_DDR1 dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU clk: sunxi-ng: v3s: add Allwinner V3 support dt-bindings: vendor-prefixes: add SoChip ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs dt-bindings: vendor-prefixes: add Sipeed dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 .../devicetree/bindings/arm/sunxi.yaml | 5 + .../clock/allwinner,sun4i-a10-ccu.yaml | 1 + .../pinctrl/allwinner,sunxi-pinctrl.txt | 2 + .../devicetree/bindings/vendor-prefixes.yaml | 4 + arch/arm/boot/dts/Makefile | 1 + .../boot/dts/sun8i-s3-lichee-zero-plus.dts | 8 + .../dts/sun8i-s3-s3l-lichee-zero-plus.dtsi | 39 +++ arch/arm/boot/dts/sun8i-s3.dtsi | 6 + arch/arm/boot/dts/sun8i-s3l.dtsi | 6 + arch/arm/boot/dts/sun8i-v3.dtsi | 14 + drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 244 +++++++++++++++- drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 6 +- drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 265 +++++++++++++++++- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 + include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 + include/dt-bindings/reset/sun8i-v3s-ccu.h | 3 + 16 files changed, 597 insertions(+), 13 deletions(-) create mode 100644 arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts create mode 100644 arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi create mode 100644 arch/arm/boot/dts/sun8i-s3.dtsi create mode 100644 arch/arm/boot/dts/sun8i-s3l.dtsi create mode 100644 arch/arm/boot/dts/sun8i-v3.dtsi