[v3,0/2] arm64: Relax ICC_PMR_EL1 synchronisation when possible

Message

Marc Zyngier Oct. 2, 2019, 9:06 a.m. UTC

This is a very late update on [1], fixing the 32bit compilation issue that
was present in v2, and adding an extra message in the kernel log to find out
what is going on.

[1] http://lore.kernel.org/r/[e-mail]

Marc Zyngier (2):
  arm64: Relax ICC_PMR_EL1 accesses when ICC_CTLR_EL1.PMHE is clear
  arm64: Document ICC_CTLR_EL3.PMHE setting requirements

 Documentation/arm64/booting.rst    |  3 +++
 arch/arm64/include/asm/barrier.h   | 12 ++++++++++++
 arch/arm64/include/asm/daifflags.h |  3 ++-
 arch/arm64/include/asm/irqflags.h  | 19 ++++++++++---------
 arch/arm64/include/asm/kvm_host.h  |  3 +--
 arch/arm64/kernel/entry.S          |  6 ++++--
 arch/arm64/kvm/hyp/switch.c        |  4 ++--
 drivers/irqchip/irq-gic-v3.c       | 20 ++++++++++++++++++++
 include/linux/irqchip/arm-gic-v3.h |  2 ++
 9 files changed, 56 insertions(+), 16 deletions(-)

Comments

Catalin Marinas Oct. 15, 2019, 5:30 p.m. UTC | #1

On Wed, Oct 02, 2019 at 10:06:11AM +0100, Marc Zyngier wrote:
> This is a very late update on [1], fixing the 32bit compilation issue that
> was present in v2, and adding an extra message in the kernel log to find out
> what is going on.
> 
> [1] http://lore.kernel.org/r/[e-mail]
> 
> Marc Zyngier (2):
>   arm64: Relax ICC_PMR_EL1 accesses when ICC_CTLR_EL1.PMHE is clear
>   arm64: Document ICC_CTLR_EL3.PMHE setting requirements

Queued for 5.5. Thanks.