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Sun, 03 Nov 2019 12:33:44 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?=27Uwe_Kleine-K?= =?utf-8?q?=C3=B6nig=27?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai Subject: [PATCH v2 0/7] Add support for H6 PWM Date: Sun, 3 Nov 2019 21:33:27 +0100 Message-Id: <20191103203334.10539-1-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191103_123350_907468_6C1C8870 X-CRM114-Status: GOOD ( 16.73 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:444 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (peron.clem[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-pwm@vger.kernel.org, =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Hi, This is a rework of Jernej's previous work[1] taking account all the previous remarks. Bindings is still strict but probe in the driver are now optionnals. If someone could confirm that the PWM is not broken, as my board doesn't output it. I didn't add the acked-tags as there are big changes. Thanks, Clément Jernej's cover: Allwinner H6 SoC has PWM core which is basically the same as that found in A20, it's just depends on additional bus clock and reset line. This series adds support for it and extends PWM driver functionality in a way that it's now possible to bypass whole core and output PWM source clock directly as a PWM signal. This functionality is needed by AC200 chip, which is bundled in same physical package as H6 SoC, to serve as a clock source of 24 MHz. AC200 clock input pin is bonded internally to the second PWM channel. I would be grateful if anyone can test this patch series for any kind of regression on other SoCs. [1]: https://patchwork.kernel.org/cover/11061737/ Changes in v2: - Remove allOf in Documentation - Add H6 example in Documentation - Change clock name from "pwm" to "mod" - Change reset quirk to optional probe - Change bus_clock quirk to optional probe - Add limitation comment about mod_clk_output - Add quirk for mod_clk_output - Change bypass formula Clément Péron (1): [DO NOT MERGE] arm64: allwinner: h6: enable Beelink GS1 PWM Jernej Skrabec (6): dt-bindings: pwm: allwinner: Add H6 PWM description pwm: sun4i: Add an optional probe for reset line pwm: sun4i: Add an optional probe for bus clock pwm: sun4i: Add support to output source clock directly pwm: sun4i: Add support for H6 PWM arm64: dts: allwinner: h6: Add PWM node .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 45 ++++++- .../dts/allwinner/sun50i-h6-beelink-gs1.dts | 4 + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++ drivers/pwm/pwm-sun4i.c | 116 +++++++++++++++++- 4 files changed, 171 insertions(+), 4 deletions(-)