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[84.217.220.205]) by smtp.gmail.com with ESMTPSA id b28sm4595260ljp.9.2019.11.25.06.25.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Nov 2019 06:25:12 -0800 (PST) From: Niklas Cassel To: linux-arm-msm@vger.kernel.org Subject: [PATCH v2 0/5] DTS changes to support cpufreq on QCS404 Date: Mon, 25 Nov 2019 15:25:05 +0100 Message-Id: <20191125142511.681149-1-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191125_062515_120014_90945298 X-CRM114-Status: UNSURE ( 9.61 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:144 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, amit.kucheria@linaro.org, bjorn.andersson@linaro.org, Niklas Cassel , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The following DTS changes are required to enable cpufreq support on the QCS404. Changes since v1: -Added a cover-letter. -Swapped order of "pll" and "aux" clocks, in order to not break DT backwards compatibility. (In case no clock-names are given, "pll" still has to be the first clock). -Removed incorrect newline in the middle of the cpu0 DT node. (This extra newline must have been added by mistake, since no other cpuX node in the same cluster had this extra newline added.) Jorge Ramirez-Ortiz (5): arm64: dts: qcom: msm8916: Add the clocks for the APCS mux/divider arm64: dts: qcom: qcs404: Add HFPLL node arm64: dts: qcom: qcs404: Add the clocks for APCS mux/divider arm64: dts: qcom: qcs404: Add DVFS support arm64: defconfig: Enable HFPLL arch/arm64/boot/dts/qcom/msm8916.dtsi | 3 +- arch/arm64/boot/dts/qcom/qcs404.dtsi | 42 +++++++++++++++++++++++++++ arch/arm64/configs/defconfig | 1 + 3 files changed, 45 insertions(+), 1 deletion(-)