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Thu, 02 Jul 2020 13:16:57 -0700 (PDT) From: Tomasz Nowicki To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, gregory.clement@bootlin.com, robh+dt@kernel.org, hannah@marvell.com Subject: [PATCH v3 0/4] Add system mmu support for Armada-806 Date: Thu, 2 Jul 2020 22:16:29 +0200 Message-Id: <20200702201633.22693-1-tn@semihalf.com> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200702_161702_575157_0A8270DF X-CRM114-Status: GOOD ( 10.32 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:144 listed in] [list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, nadavh@marvell.com, iommu@lists.linux-foundation.org, Tomasz Nowicki , mw@semihalf.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org There were already two versions of series to support SMMU for AP806, including workaround for accessing ARM SMMU 64bit registers. First [1] by Hanna Hawa and second [2] by Gregory CLEMENT. Since it got stuck this is yet another try. I incorporated the V2 comments, mainly by moving workaround code to arm-smmu-impl.c as requested. For the record, AP-806 can't access SMMU registers with 64bit width, this patches split the readq/writeq into two 32bit accesses instead and update DT bindings. The series was successfully tested on a vanilla v5.8-rc3 kernel and Intel e1000e PCIe NIC. The same for platform devices like SATA and USB. [1]: https://lkml.org/lkml/2018/10/15/373 [2]: https://lkml.org/lkml/2019/7/11/426 Hanna Hawa (1): iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum #582743 Marcin Wojtas (1): arm64: dts: marvell: add SMMU support Tomasz Nowicki (2): iommu/arm-smmu: Add SMMU ID2 register fixup hook dt-bindings: arm-smmu: add compatible string for Marvell Armada-AP806 SMMU-500 Documentation/arm64/silicon-errata.rst | 3 ++ .../devicetree/bindings/iommu/arm,smmu.yaml | 5 ++ arch/arm64/boot/dts/marvell/armada-8040.dtsi | 36 +++++++++++++ arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 17 ++++++ drivers/iommu/arm-smmu-impl.c | 52 +++++++++++++++++++ drivers/iommu/arm-smmu.c | 3 ++ drivers/iommu/arm-smmu.h | 1 + 7 files changed, 117 insertions(+)