From patchwork Tue Jul 7 15:21:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sven Auhagen X-Patchwork-Id: 11648915 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E989E14E3 for ; Tue, 7 Jul 2020 15:23:23 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B5CFA2065D for ; Tue, 7 Jul 2020 15:23:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="hMEMDyM6"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=voleatech.de header.i=@voleatech.de header.b="U2jVEwyO" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B5CFA2065D Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=voleatech.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=NZT/vIoY6bgCZkJL6z1eAa30zOaKqN/SWezrdIG0ZYg=; b=hMEMDyM6NgzXvzbcOPl0jXYeXX dzIuKGeg3ZMNFh6lAuwyR026ikNBbA9hjnKjyzcBBbhYMtHlxWCdWqlvonCLDNNgkal82TtWKUtty PPAsTK8q1t9Asn6CatlbOm6rYnA96r4YLAEZr4UpVuR49VDK3YCGGykAhpA9X9Umr0NNwLOhgM4yA 38DVvGiYwD897ks/DTtTiBXP54cNDzodvdq4RO+Ukc7jQ1fefwFQIZc/5rOKbCd4bSCHrgwqRmgWr s1Z9PZhqFcdz31ZGJ56Bs+xvGBDW9iH/BbK1p0SGebDr2gheZzVK1y71WaLyks3Tk+3GpJOM4mTiq ah+PD/8A==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jspPa-0005gF-Vo; Tue, 07 Jul 2020 15:21:35 +0000 Received: from mail-db8eur05on2119.outbound.protection.outlook.com ([40.107.20.119] helo=EUR05-DB8-obe.outbound.protection.outlook.com) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jspPW-0005ec-VG for linux-arm-kernel@lists.infradead.org; Tue, 07 Jul 2020 15:21:32 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Ohen190HKvG31cX+PyCfmpAFid1h1m8r5Qe/v3KcmZhT/BBx7P1aK8v/M/8vrZn5Q9E58On/ExwNJ25UFtxn8Bi46rQQpE8FVVZucUxcGD3Du1lcD2dyXma8CFWs4ZHEgWdECAxGVpT7pd9ue5JNmROubRjb+EGM5TtJBDA2QhE9lh9MQYcpoKrFX3ZU5B+vtrAk1Hab0R9ldXAV/5GG+yn4xUsj0bcb9uhYiR9fBaOXhy5woQSbbF69zV75ENKr5f6LhnejNF9nBHxREWY4j7q6iF0oWUssTtY95L16yyftdYGtJ52kYgLG4nwwZgVSmsf2esZYm7miYy2klhFKNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0YIc9iLPp7EuDfHQ3ZYst437lotFmGLF5yaI6epJnw4=; b=EOpsshgQmxTTU5sSzJEfEO0adAyrUcptxSWthhMtOM/MJgFM1Fmed8k67kzFYocWAfjL0zdCMugwajUfhVNQyp++z31TdmYh+EyrhNm/Qqb6HB+t534cRezsSOPvsMBEGk4rEjagX32iW9WVUKPE0SjF/2m1Y1smp4pL88j24uqwyIyks1qJ5RwjnuhVLzWb59FW6ErqjytleSs7bBe+XBDTD5zfda6eA14a5wGOa0blEabWTLlGz8lCBWOAWjFRGyRmTKsNhr7+kmCWIL6mVdtPZi/FguXH76WNQmxhDcBEuwVLnxYolmBbp3iYpWAVE4oxAlHx/oVhgyc71crgAw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=voleatech.de; dmarc=pass action=none header.from=voleatech.de; dkim=pass header.d=voleatech.de; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=voleatech.de; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0YIc9iLPp7EuDfHQ3ZYst437lotFmGLF5yaI6epJnw4=; b=U2jVEwyOnX2gYEC+EGnExHLO/czAY+iZMtE+I7xXwYu4hJQAIbxpx/WN0ShvycIrdEGBbNCIFZz3Yxpi0BV42dxpSL3/MScMse1PPlR9iUA4g0FkdPT8nw78xEl/UoJg12euqqMBjIc3wfmG81D1j49V4SikQPabrhAubjtNmWk= Authentication-Results: lists.infradead.org; dkim=none (message not signed) header.d=none;lists.infradead.org; dmarc=none action=none header.from=voleatech.de; Received: from AM4PR0501MB2785.eurprd05.prod.outlook.com (2603:10a6:200:5d::11) by AM0PR05MB4226.eurprd05.prod.outlook.com (2603:10a6:208:57::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3153.27; Tue, 7 Jul 2020 15:21:26 +0000 Received: from AM4PR0501MB2785.eurprd05.prod.outlook.com ([fe80::39a1:e237:5fef:6f39]) by AM4PR0501MB2785.eurprd05.prod.outlook.com ([fe80::39a1:e237:5fef:6f39%11]) with mapi id 15.20.3153.029; Tue, 7 Jul 2020 15:21:26 +0000 From: sven.auhagen@voleatech.de To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 0/7] Armada8k enable per-port SATA interrupts and drop a hack in the IRQ subsystem Date: Tue, 7 Jul 2020 17:21:07 +0200 Message-Id: <20200707152114.53890-1-sven.auhagen@voleatech.de> X-Mailer: git-send-email 2.24.3 (Apple Git-128) X-ClientProxiedBy: AM0PR04CA0006.eurprd04.prod.outlook.com (2603:10a6:208:122::19) To AM4PR0501MB2785.eurprd05.prod.outlook.com (2603:10a6:200:5d::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from SvensMacBookAir.sven.lan (109.193.235.168) by AM0PR04CA0006.eurprd04.prod.outlook.com (2603:10a6:208:122::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3174.20 via Frontend Transport; Tue, 7 Jul 2020 15:21:26 +0000 X-Mailer: git-send-email 2.24.3 (Apple Git-128) X-Originating-IP: [109.193.235.168] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ac9dc01e-c071-46b7-f5f2-08d822896a72 X-MS-TrafficTypeDiagnostic: AM0PR05MB4226: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-Forefront-PRVS: 0457F11EAF X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: y14EG7a4JhGKNN/XduckI68jRC1h+6PWBDLLTHL8eL6KXDSh1YYiC0PDQZOc31FP4DwRPCoE+GaKS46FGwul+S+f3znBzN/ma/prA3XcK3AEniodJKV8sAI5BNQYCbxeZLHxEEI28BxR/52Lwtxgo1mxzqSciCfmMR5wf5DSlBDOHyoL2heWsTHAa6zMxQlVuBRlvs2j6k+SkmuJ1rgTij0AxlZS0begVS02+UL0IJb8sjAA659jaVCIllsKIragH9FrKegAFJQJZvZ5R0k2qvzIGq7YcCfVjDR/+6xlq+2EqFfYXTf+P/KulrTZcMorgyRz4ZYnFQrBN+AFWCmkhOJAgBm0LqkRbwAeO+4OFP1Q55PFpi+oxgZ5FuIZKdoP X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM4PR0501MB2785.eurprd05.prod.outlook.com; PTR:; CAT:NONE; SFTY:; SFS:(4636009)(396003)(346002)(39830400003)(376002)(366004)(136003)(6916009)(5660300002)(83380400001)(86362001)(508600001)(6486002)(6666004)(4326008)(66574015)(36756003)(316002)(956004)(2616005)(186003)(16526019)(52116002)(8936002)(8676002)(66476007)(66946007)(6512007)(1076003)(9686003)(2906002)(6506007)(26005)(66556008)(32563001); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: 5fU7//SszqG1bPI3lFfGY36ExB0RQdZ0ye7s1ckJHJInx/Xcd3nA/5uUD8KzHEiHGPITHAP9Ppa5p86zJ0aNOPg3X3T29WmOMYF/o6gXykMgPHOYT5chFeAQGO/iPGzOnN6BhmKTnM/kYxyDiw6zaX4E7ajJVFZuiJM5XEjhLFlXXShgEeLzzGeqeUPLjdNCpGFXZZ8t8qoAvm/9bCwIk50MLuEDC3Sl1aGY9cwN3gbZZyVgAsh2/R/fDtnwMcTD1idH0VCxMdOGsm6U/ys/xkCGQlXX/iXr1yn5SOonLoRIMpwxG1iSFo897zTquR3YaJgaWsGtqPBONiTCfwnMhrTY6LS01KIfbIL702Dmc3p8FAdusPfgETGNaun0wUxwdCxe/VCQX4FdZUvHSFXG2kSQ4/xQJXFSgdoo3gyQRPFjWCNN91Rc2GtN7I1n6dE1t408nzVyJdq8BYrDRzlSUVCpd4bSVHOAovfmVNBOJQn7a/0GKHnXurM7Rmnl/CxH X-OriginatorOrg: voleatech.de X-MS-Exchange-CrossTenant-Network-Message-Id: ac9dc01e-c071-46b7-f5f2-08d822896a72 X-MS-Exchange-CrossTenant-AuthSource: AM4PR0501MB2785.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jul 2020 15:21:26.6757 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b82a99f6-7981-4a72-9534-4d35298f847b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: oOcGIC3Vlh6iBcm5Vh7fpLGxkRCeWLJA2plhp0Ulgzv60Yefpap8K6GXK9sQ0oTyRU/ENZvxT5/+3o2VqmMlEycz0+R/NwC57oaSPJ/doPs= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR05MB4226 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200707_112131_214750_B602B1FD X-CRM114-Status: GOOD ( 17.24 ) X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [40.107.20.119 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [40.107.20.119 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.0 MSGID_FROM_MTA_HEADER Message-Id was added by a relay X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: baruch@tkos.co.il, antoine.tenart@bootlin.com, maxime.chevallier@bootlin.com, nadavh@marvell.com, thomas.petazzoni@bootlin.com, miquel.raynal@bootlin.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Sven Auhagen Hello, there were already 4 versions of this series from Miquèl. I talked to Miquèl and I fixed up the last comments from v4. I am looking for feedback if this patch series is now ready to be merged and what should be further changed. Here is the original cover letter: Some time ago, when the initial support for Armada CP110 was contributed, the SATA core was not able to handle per-port interrupts. Despite the hardware reality, the device tree only represents one main interrupt for the two ports. Having both SATA ports enabled at the same time has been achieved by a hack in the ICU driver(1) that faked the use of the two interrupts, no matter which SATA port was in use. Now that the SATA core is ready to handle more than one interrupt, this series adds support for it in the libahci_platform code. The CP110 device tree must be updated to reflect the two SATA ports available and their respective interrupts. To do not break DT backward compatibility, the ahci_platform driver now embeds a special quirk which checks if the DT is valid (only for A8k compatible) and, if needed, creates the two missing sub-nodes, and assign them the relevant "reg" and "interrupts" properties, before removing the main SATA node "interrupts" one. (1) The ICU is an irqchip aggregating the CP110 (south-bridge) interrupts into MSIs for the AP806 (north-bridge). Best Sven Changes in v5 ============= * Rebase on top of v5.8-rc3 * Move code to ahci mvebu and use custom functions Changes in v4 ============= * Rebase on top of v5.2-rc1 * s/ARM64/arm64/ in the DT change commit title. Changes in v3 ============= * Removed useless locking when acking the SATA host IRQ_STAT bit. * As spotted by Hans, do not enable the AHCI_HFLAG_MULTI_MSI flag only if more than one port is enabled, DTs might declare only one interrupt and have multiple ports. Added Hans' Reviewed-by tag. * Added Rob's Reviewed-by tags. * Added explicit references to the 'Device Tree' being the culprit for the hacks which are being treated in patch "ata: ahci: mvebu: Add support for A8k legacy bindings" as suggested by Marc. * Modified all DTs to avoid enabling/disabling the SATA ports independently, which does not work. Either both ports are enabled, or none. Tested on MacchiatoBin that all three availabe ports on the board are functional. Changes in v2 ============= * In the AHCI world, the 'irq' is now an '*irqs' array, I ensured it is allocated even when not using *_platform drivers. * Moved the whole logic from the generic ahci_platform.c driver to the Marvell's ahci_mvebu.c driver. * Dropped the whole DT manipulation quirk. * Instead used a hack to configure both interrupts when using the deprecated bindings, this hack is a8k specific but there is a flag that is passed to the core during the ahci_platform_get_resources() to indicate that the number of ports must be forced to 2 no matter the number of child nodes. * The A8k based Clearfog-GT actually uses the SATA IP (Baruch's info) so do not remove the SATA node from the DT. Instead, change the DTS to fit the new bindings (the board only uses the second port at offset 1). * Added bindings documentation about the A8k AHCI compatible (existing in DTs, missing in the doc). * SATA Sub-nodes representing ports already are documented, I just added a mention that they can also have an interrupts property which is mutually exclusive with the root SATA node. Miquel Raynal (5): ata: ahci: mvebu: Rename a platform data flag ata: ahci: mvebu: Support A8k compatible irqchip/irq-mvebu-icu: Remove the double SATA ports interrupt hack dt-bindings: ata: Update ahci bindings with possible per-port interrupts dt-bindings: ata: Update ahci_mvebu bindings Sven Auhagen (2): ata: ahci: mvebu: Add support for A8k legacy DT bindings arm64: dts: marvell: armada-cp110: Switch to per-port SATA interrupts .../devicetree/bindings/ata/ahci-platform.txt | 7 + arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 6 +- drivers/ata/ahci.h | 3 + drivers/ata/ahci_mvebu.c | 254 +++++++++++++++++- drivers/ata/libahci.c | 3 +- drivers/ata/libahci_platform.c | 3 + drivers/irqchip/irq-mvebu-icu.c | 18 -- include/linux/ahci_platform.h | 1 + 8 files changed, 265 insertions(+), 30 deletions(-)