From patchwork Wed Jul 8 05:00:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Reddy X-Patchwork-Id: 11650627 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B3CB413B4 for ; Wed, 8 Jul 2020 05:03:19 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8CFE820786 for ; Wed, 8 Jul 2020 05:03:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="kc/f87CK"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="qgWKt/Hl" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8CFE820786 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=cRj2qjc38MQNPY+DKWGEGBS0t6x65y5k1ILKpSff6l8=; b=kc/f87CKHvl1LC3MxX4jIuvTd8 31Hy9U/nzDFTNhpRr4/2NF7JTQoTYRzF80U4dMIvlEV8dgQ0ggJpYKYjajKEGQMPLOxcWJXQLFdMj 1pAum7yePSOkCiURUdv3MwRh4k//271dZ+/7YzVBFEx4NZKb99zlr6kWLXVowtbxXHjOpxtFYQadR 1zJymS0CR32HlbxrTqjmA3+bi/RRP268PNy/ZjXXJnIopGLpqyH1bmb+DS98AnBT4jrB3R6VzjozO WuWeBDP/XC33MgEWvWJMvzG4SW/9INtMRP/peEpM1rBL3NIi6Wy86xEGw+wg8QjX4PP9G+iE+X1Nv joqMtYfw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jt2CL-0003l9-HE; Wed, 08 Jul 2020 05:00:45 +0000 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jt2Bw-0003b5-Gs for linux-arm-kernel@lists.infradead.org; Wed, 08 Jul 2020 05:00:23 +0000 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 07 Jul 2020 21:59:23 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 07 Jul 2020 22:00:17 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 07 Jul 2020 22:00:17 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 8 Jul 2020 05:00:13 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 8 Jul 2020 05:00:13 +0000 Received: from vdumpa-ubuntu.nvidia.com (Not Verified[172.17.173.140]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 07 Jul 2020 22:00:13 -0700 From: Krishna Reddy To: , , , , , Subject: [PATCH v10 0/5] NVIDIA ARM SMMU Implementation Date: Tue, 7 Jul 2020 22:00:12 -0700 Message-ID: <20200708050017.31563-1-vdumpa@nvidia.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1594184363; bh=+VIMULVcX/VU6BtBuWewZbJl68Bh+UrUfFfMcAm4UI4=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: MIME-Version:X-NVConfidentiality:Content-Transfer-Encoding: Content-Type; b=qgWKt/HlteNBV+Xgo/IPryofk7LkeQfjTY6lpdJ6OV//R8I1OutMYPX+GjWXuwkCV JXwq2R7CgE1k3tgTZoCQraHRxz5Fnjxwg/wqbsWFCc4DdFiv70IU7UUF5CXWpCTi1A dRSLY/QSLQATnzDTAEncddPo7o6ooPmHmTwffnCfhKVzi6mxHDseXQ7czVi47MkXtQ 6QynXZNc6Q9DokeafjZvk2ByvkHtIY1S1l0HwYQzkIsaTLFsOfpyibiYa2kunp61QO L2lRiD/w6HMfj6dS9CD8kRiqfue9YHsP3XKc5y9fXCwinIVMg83WnfJmAhp19Mnhhh 0iLrz7b5ePFww== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200708_010020_680436_ABB6C30F X-CRM114-Status: UNSURE ( 9.24 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [216.228.121.64 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.0 DKIMWL_WL_HIGH DKIMwl.org - Whitelisted High sender X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: snikam@nvidia.com, devicetree@vger.kernel.org, nicoleotsuka@gmail.com, mperttunen@nvidia.com, bhuntsman@nvidia.com, yhsu@nvidia.com, linux-kernel@vger.kernel.org, talho@nvidia.com, iommu@lists.linux-foundation.org, nicolinc@nvidia.com, linux-tegra@vger.kernel.org, praithatha@nvidia.com, linux-arm-kernel@lists.infradead.org, bbiswas@nvidia.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Changes in v10: Perform SMMU base ioremap before calling implementation init. Check for Global faults across both ARM MMU-500s during global interrupt. Check for context faults across all contexts of both ARM MMU-500s during context fault interrupt. Add new DT binding nvidia,smmu-500 for NVIDIA implementation. v9 - https://lkml.org/lkml/2020/6/30/1282 v8 - https://lkml.org/lkml/2020/6/29/2385 v7 - https://lkml.org/lkml/2020/6/28/347 v6 - https://lkml.org/lkml/2020/6/4/1018 v5 - https://lkml.org/lkml/2020/5/21/1114 v4 - https://lkml.org/lkml/2019/10/30/1054 v3 - https://lkml.org/lkml/2019/10/18/1601 v2 - https://lkml.org/lkml/2019/9/2/980 v1 - https://lkml.org/lkml/2019/8/29/1588 Krishna Reddy (5): iommu/arm-smmu: move TLB timeout and spin count macros iommu/arm-smmu: ioremap smmu mmio region before implementation init iommu/arm-smmu: add NVIDIA implementation for ARM MMU-500 usage dt-bindings: arm-smmu: add binding for Tegra194 SMMU iommu/arm-smmu: Add global/context fault implementation hooks .../devicetree/bindings/iommu/arm,smmu.yaml | 18 ++ MAINTAINERS | 2 + drivers/iommu/Makefile | 2 +- drivers/iommu/arm-smmu-impl.c | 3 + drivers/iommu/arm-smmu-nvidia.c | 278 ++++++++++++++++++ drivers/iommu/arm-smmu.c | 29 +- drivers/iommu/arm-smmu.h | 6 + 7 files changed, 328 insertions(+), 10 deletions(-) create mode 100644 drivers/iommu/arm-smmu-nvidia.c base-commit: e5640f21b63d2a5d3e4e0c4111b2b38e99fe5164