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IronPort-SDR: jG1OkJTaODSRQIiJ7KNJRpIPabU+a8Vl54DQuV86wndtUUn3nOJjrMJRxbDf3qn2wpMV9TkyNM fnBjVjEK8p8w97YVQYnaUvntqNis2x9I5f0YgtYDVkV85kyoT0i4giwWt5AiIg5RPNotiB7E64 OV02y/7XPEW1tmd6ccZzldOkCXo2SOx7kRtHc8iIaj7QY2Scsc69Dsx8lKoyxKqFZlNkpHEXOZ 3OIhW12jqMoe89e2z9NaS95IXCHL9fbs7/qn0XN8TpoaIaWTg9cFq+Rmlb/CrKwD33P7ay0wHS FJw= X-IronPort-AV: E=Sophos;i="5.75,390,1589266800"; d="scan'208";a="85239319" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 24 Jul 2020 04:14:17 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 24 Jul 2020 04:14:18 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 24 Jul 2020 04:13:35 -0700 From: Lars Povlsen To: Mark Brown , Peter Rosin Subject: [PATCH v4 0/6] spi: Adding support for Microchip Sparx5 SoC Date: Fri, 24 Jul 2020 13:13:58 +0200 Message-ID: <20200724111404.13293-1-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200724_071420_017935_FF111380 X-CRM114-Status: GOOD ( 11.30 ) X-Spam-Score: -2.5 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.153.233 listed in list.dnswl.org] 0.0 RCVD_IN_MSPIKE_H4 RBL: Very Good reputation (+4) [68.232.153.233 listed in wl.mailspike.net] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Serge Semin , linux-spi@vger.kernel.org, Serge Semin , Lars Povlsen , Microchip Linux Driver Support , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This is an add-on series to the main SoC Sparx5 series (Message-ID: <20200615133242.24911-1-lars.povlsen@microchip.com> The series add support for the Sparx5 SoC SPI controller in the spi-dw-mmio.c spi driver. v4 changes: - Changed snps,rx-sample-delay-ns to snps,rx-sample-delay-ns suggested by Rob Herring (rockchip also has this property). - Added support for controller-level rx-sample-delay-ns value as well as per SPI slave value (rockchip has controller-level property). - Dropped internal mux in favor of suggested spi-mux to control bus inteface selection. v3 changes: - Added mux support for controlling SPI bus interface. This is new mux driver, bindings and added to sparx5 base DT. - Removed "microchip,spi-interface2" property in favour of "mux-controls" property in SPI controller (sparx5 only). - Changed dw_spi_sparx5_set_cs() to use the mux control instead of directly acessing "mux" register. Associated code/defines moved to mux driver. - Changed dw_spi_sparx5_set_cs() to match other similar functions in signature and avoid explicit CS toggling. - Spun off duplicated NAND device DT chunks into separate DT file. v2 changes: - Moved all RX sample delay into spi-dw-core.c, using the "snps,rx-sample-delay-ns" device property. - Integrated Sparx5 support directly in spi-dw-mmio.c - Changed SPI2 configuration to per-slave "microchip,spi-interface2" property. - Added bindings to existing snps,dw-apb-ssi.yaml file - Dropped patches for polled mode and SPI memory operations. Lars Povlsen (6): spi: dw: Add support for RX sample delay register spi: dw: Add Microchip Sparx5 support arm64: dts: sparx5: Add SPI controller and associated mmio-mux dt-bindings: snps,dw-apb-ssi: Add sparx5 support, plus rx-sample-delay-ns property arm64: dts: sparx5: Add spi-nor support arm64: dts: sparx5: Add spi-nand devices .../bindings/spi/snps,dw-apb-ssi.yaml | 21 ++++++ arch/arm64/boot/dts/microchip/sparx5.dtsi | 47 ++++++++++++- .../arm64/boot/dts/microchip/sparx5_nand.dtsi | 31 ++++++++ .../boot/dts/microchip/sparx5_pcb125.dts | 30 ++++++++ .../boot/dts/microchip/sparx5_pcb134.dts | 1 + .../dts/microchip/sparx5_pcb134_board.dtsi | 16 +++++ .../boot/dts/microchip/sparx5_pcb135.dts | 1 + .../dts/microchip/sparx5_pcb135_board.dtsi | 16 +++++ drivers/spi/spi-dw-core.c | 26 +++++++ drivers/spi/spi-dw-mmio.c | 70 ++++++++++++++++++- drivers/spi/spi-dw.h | 3 + 11 files changed, 260 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/microchip/sparx5_nand.dtsi