From patchwork Wed Aug 5 11:00:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 11701747 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 81C131392 for ; Wed, 5 Aug 2020 11:01:40 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5BB0B22CAD for ; Wed, 5 Aug 2020 11:01:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="n/e33t9y"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=0x0f.com header.i=@0x0f.com header.b="EkQQ89yO" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5BB0B22CAD Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=/QH2yZlWozaiKsFHVtvsuVF9YbvA8DWqazsOzK/HaN8=; b=n/e33t9y0/ciPU9N99E6Djo09A zwPSNUifl8I/DKltkhb7lFKNufanVcE8KuO0xrTaDsAe5pzmWuMCanqPZyf6kPEc8PDMle/AbrPSp McYQS3almfmZ9yvw38LJz9UfIodfwusz8miKxgB3yJ5ygXjudnKsH726vxtkAlQZxpzFLkyLZO/zI pJjPO4AiNKJXkE2aKexXJZPaSv5VriWl7PAhHQvbiqXDZvi1nTWjXKNQMYoMC01cKbr8OJyAxS4tL wtZALrWgFN3JlJzEapYb7A03H05CoAvw72a5FUWFHABTp8t9th1meyA4eZdh6A6AjO1amd/a+dJ+o 9LIXEbfg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k3HAm-0004Ad-Lr; Wed, 05 Aug 2020 11:01:28 +0000 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1k3HAk-00049X-2W for linux-arm-kernel@lists.infradead.org; Wed, 05 Aug 2020 11:01:27 +0000 Received: by mail-pf1-x443.google.com with SMTP id 17so2130509pfw.9 for ; Wed, 05 Aug 2020 04:01:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=IXl0op0XvQYTvwb5bcKNryRkXDVpBLnZpOMVzhjZNkQ=; b=EkQQ89yOe1EY9nCbVWZoj+93xO0UKBjV3pPJai1tGnUiFF0YVCdf8dXYFZQB9ONXtR ep47VBzoQ6jmxkdmei8O1tV8rewHUskV5pgNaUV3mfnLbFe/qmGR8zOxPkqx/ZrF0iIS LOlEzVbCSII1vSt3mVT+9npv7i8tO6fEvWnA0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=IXl0op0XvQYTvwb5bcKNryRkXDVpBLnZpOMVzhjZNkQ=; b=Zj+x/luKIbUjwdqopqPr9mmTXIbdFA4qlmMGrm2fyHqvfmNpYJSJc37J27cHoa7dwG U2wnSZHPAX9V3eYx/MGc0CfN92AgSu7BgeFcddpZV1lzLrQ45gl4UErYAWgF/Z8N1Avg 3KhFVa25f8/ictpkAwbJsEVjoeH+jSkTAL8b/igQQijV+Ck4WOIJjgqXN0K/lYKTmc+5 v4gRyTBQqwJ4vDGtMJVeTgo3V+oa5p5lADz9nJ7fyx4EBXGu8sh4zyKMz2ENM8eF4yF4 b+BxUh8hqhG7vX2LQSu8v7Xx8h/q0XOzQ1MayalBO/kYHALzRbSjy9+/nArLiUeGo5sy 4uGg== X-Gm-Message-State: AOAM530JlVM5g1Op/LZHEynQ386HxSYD+z4/qhc3oV8rYVmSgejUJAbE Vy8mP8ohJrd8pH/n3ZOIuOIWevdZZpk= X-Google-Smtp-Source: ABdhPJzHQO7oRI8Z0FA40Z+RnWxDwemAbCPf5cqMPN8QdngN6CsqzLsAddBnozTIqq8fndWf2sqZew== X-Received: by 2002:a63:b74f:: with SMTP id w15mr2581625pgt.314.1596625281526; Wed, 05 Aug 2020 04:01:21 -0700 (PDT) Received: from shiro.work (p532183-ipngn200506sizuokaden.shizuoka.ocn.ne.jp. [153.199.2.183]) by smtp.googlemail.com with ESMTPSA id fv21sm2583142pjb.16.2020.08.05.04.01.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2020 04:01:20 -0700 (PDT) From: Daniel Palmer To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 0/3] irqchip: mstar: msc313 intc driver Date: Wed, 5 Aug 2020 20:00:49 +0900 Message-Id: <20200805110052.2655487-1-daniel@0x0f.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200805_070126_357061_FB0E9D30 X-CRM114-Status: GOOD ( 16.71 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:443 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, jason@lakedaemon.net, arnd@arndb.de, maz@kernel.org, Daniel Palmer , linux-kernel@vger.kernel.org, robh+dt@kernel.org, tglx@linutronix.de Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This driver adds support for the interrupt controllers present between the various IP blocks and the ARM GIC in MStar/SigmaStar Armv7 SoCs. All of the chips so far have two instances of this controller. One instance controls what are called "IRQ" interrupts by the vendor code I have seen. The other instance controls what are called "FIQ" interrupts by the vendor code. Presumably because they can be FIQ interrupts. Right now the FIQ bypass is disabled in the GIC so they operate just the same as the IRQ interrupts. The register layouts are the same for both. The FIQ one needs to have the status bit cleared on EOI so that difference is handled by a compatible string difference. I initially made this an RFC because this is my first interrupt controller driver and I expect to have made a bunch of mistakes. I've cleaned this up a bit since then but I still expect it's not 100% correct. Especially the offset to map the INTC interrupt to the GIC interrupt. Daniel Palmer (3): dt: bindings: interrupt-controller: Add binding description for msc313-intc irqchip: mstar: msc313-intc interrupt controller driver ARM: mstar: Add interrupt controller to base dtsi .../mstar,msc313-intc.yaml | 79 +++++++ MAINTAINERS | 2 + arch/arm/boot/dts/mstar-v7.dtsi | 20 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-msc313-intc.c | 210 ++++++++++++++++++ 5 files changed, 312 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mstar,msc313-intc.yaml create mode 100644 drivers/irqchip/irq-msc313-intc.c