[0/4] arm64: cppc: add FFH support using AMUs

Message

Ionela Voinescu Aug. 26, 2020, 1:03 p.m. UTC

Hi guys,

This series adds support for CPPC's delivered and reference performance
counters through the FFH methods by using the AMU equivalent core and
constant cycle counters.

This support is added in patch 4/4, while the first 3 patches generalise
the existing AMU counter read and validation functionality to be reused
for this usecase.

The specification that drove this implementation can be found at [1],
chapter 3.2.

The code was tested on a Armv8-A Base Platform FVP: Architecture Envelope
Model [2] with the following _CPC entry for all CPUs:

Name(_CPC, Package()
{
  23, // NumEntries
  3, // Revision
  100, // Highest Performance - Fixed 100MHz
  100, // Nominal Performance - Fixed 100MHz
  1, // Lowest Nonlinear Performance
  1, // Lowest Performance
  ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Guaranteed Performance Register
  ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Desired Perf Register
  ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Minimum Performance Register
  ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Maximum Performance Register
  ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Red. Tolerance Register
  ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Time Window Register
  ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Counter Wraparound Time
  ResourceTemplate(){Register(FFixedHW, 0x40, 0, 1, 0x4)}, // Reference Performance Counter Register
  ResourceTemplate(){Register(FFixedHW, 0x40, 0, 0, 0x4)}, // Delivered Performance Counter Register
  ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Performance Ltd Register
  ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // CPPC Enable Register
  ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Selection Enable
  ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Autonomous Activity Window Register
  ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, // Energy Performance Preference Register
  100, // Reference Performance - Fixed 100MHz
  1, // Lowest Frequency
  100, // Nominal Frequency - Fixed 100MHz
})

The following configuration is necessary for Activity Monitors use:

   cluster0.has_arm_v8-4=1
   cluster1.has_arm_v8-4=1
   cluster0.has_amu=1
   cluster1.has_amu=1

To be noted:
 - The FVP has fixed core and constant frequency of 100MHz
 - The kernel I used for testing had some extra debug information as you
   can see below:

$ cat /sys/devices/system/cpu/cpufreq/policy*/cpuinfo_cur_freq
[   23.850590] CPPC: Delivered perf (core_cnt*ref_perf/const_cnt): (2402*100)/2402=100.
100000
[   23.851246] CPPC: Delivered perf (core_cnt*ref_perf/const_cnt): (2402*100)/2402=100.
100000
[   23.851826] CPPC: Delivered perf (core_cnt*ref_perf/const_cnt): (2873*100)/2872=100.
100000
[   23.852326] CPPC: Delivered perf (core_cnt*ref_perf/const_cnt): (2402*100)/2402=100.
100000
[   23.852747] CPPC: Delivered perf (core_cnt*ref_perf/const_cnt): (2309*100)/2309=100.
100000
[   23.853228] CPPC: Delivered perf (core_cnt*ref_perf/const_cnt): (1333*100)/1333=100.
100000
[   23.854097] CPPC: Delivered perf (core_cnt*ref_perf/const_cnt): (18762*100)/20003=93.
93000
[   23.854890] CPPC: Delivered perf (core_cnt*ref_perf/const_cnt): (20047*100)/20051=99.
99000

[1] https://documentation-service.arm.com/static/5f106ad60daa596235e80081
[2] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms

Thanks,
Ionela.

Ionela Voinescu (4):
  arm64: cpufeature: restructure AMU feedback function
  arm64: wrap and generalise counter read functions
  arm64: split counter validation function
  arm64: implement CPPC FFH support using AMUs

 arch/arm64/include/asm/cpufeature.h |   6 +-
 arch/arm64/kernel/cpufeature.c      |  15 ++-
 arch/arm64/kernel/topology.c        | 147 ++++++++++++++++++++++------
 3 files changed, 129 insertions(+), 39 deletions(-)


base-commit: 3a00d3dfd4b68b208ecd5405e676d06c8ad6bb63