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Thu, 10 Sep 2020 06:54:48 -0400 (EDT) From: Andrew Jeffery To: linux-mmc@vger.kernel.org Subject: [PATCH 0/3] mmc: sdhci-of-aspeed: Expose data sample phase delay tuning Date: Thu, 10 Sep 2020 20:24:37 +0930 Message-Id: <20200910105440.3087723-1-andrew@aj.id.au> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200910_065456_151408_C3A5FC44 X-CRM114-Status: UNSURE ( 9.85 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.9 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [66.111.4.28 listed in list.dnswl.org] 0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [66.111.4.28 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, ulf.hansson@linaro.org, linux-aspeed@lists.ozlabs.org, adrian.hunter@intel.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, joel@jms.id.au, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Hello, This series exposes some devicetree properties for tuning sample phase delay in the Aspeed SD/eMMC controllers. The relevant register was introduced on the AST2600 and is present for both the SD/MMC controller and the dedicated eMMC controller. Please review! Joel: If Rob's happy with the binding change can you take the dts patch through the aspeed dt tree? Cheers, Andrew Andrew Jeffery (3): dt: bindings: mmc: Add phase control properties for the Aspeed SDHCI mmc: sdhci-of-aspeed: Expose data sample phase delay tuning ARM: dts: tacoma: Add data sample phase delay for eMMC .../devicetree/bindings/mmc/aspeed,sdhci.yaml | 8 + arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 2 + drivers/mmc/host/sdhci-of-aspeed.c | 137 +++++++++++++++++- 3 files changed, 142 insertions(+), 5 deletions(-)