[v2,0/2] arm64/mm: Enable color zero pages

Message

Gavin Shan Sept. 23, 2020, 5:37 a.m. UTC

The feature of color zero pages isn't enabled on arm64, meaning all
read-only (anonymous) VM areas are backed up by same zero page. It
leads pressure to L1 (data) cache on reading data from them. This
tries to enable color zero pages.

PATCH[1/2] decouples the zero PGD table from zero page
PATCH[2/2] allocates the needed zero pages according to L1 cache size

Changelog
=========
v2:
   * Rebased to 5.9.rc6                                      (Gavin)
   * Retrieve cache topology from ACPI/DT                    (Will/Robin)

Gavin Shan (2):
  arm64/mm: Introduce zero PGD table
  arm64/mm: Enable color zero pages

 arch/arm64/include/asm/cache.h       |  3 ++
 arch/arm64/include/asm/mmu_context.h |  6 +--
 arch/arm64/include/asm/pgtable.h     | 11 ++++-
 arch/arm64/kernel/cacheinfo.c        | 67 ++++++++++++++++++++++++++++
 arch/arm64/kernel/setup.c            |  2 +-
 arch/arm64/kernel/vmlinux.lds.S      |  4 ++
 arch/arm64/mm/init.c                 | 37 +++++++++++++++
 arch/arm64/mm/mmu.c                  |  7 ---
 arch/arm64/mm/proc.S                 |  2 +-
 drivers/base/cacheinfo.c             |  3 +-
 include/linux/cacheinfo.h            |  6 +++
 11 files changed, 132 insertions(+), 16 deletions(-)

Comments

Catalin Marinas Sept. 23, 2020, 8:43 a.m. UTC | #1

Hi Gavin,

On Wed, Sep 23, 2020 at 03:37:19PM +1000, Gavin Shan wrote:
> The feature of color zero pages isn't enabled on arm64, meaning all
> read-only (anonymous) VM areas are backed up by same zero page. It
> leads pressure to L1 (data) cache on reading data from them. This
> tries to enable color zero pages.
> 
> PATCH[1/2] decouples the zero PGD table from zero page
> PATCH[2/2] allocates the needed zero pages according to L1 cache size

To save you (and potential reviewers) some time, please include in the
cover letter details of a realistic workload/benchmark that is improved
by this patchset, backed by numbers. Just because it's doable and the
patches aren't too complex is not a good enough reason for merging.

Thanks.

Gavin Shan Sept. 23, 2020, 10:47 p.m. UTC | #2

Hi Catalin,

On 9/23/20 6:43 PM, Catalin Marinas wrote:
> On Wed, Sep 23, 2020 at 03:37:19PM +1000, Gavin Shan wrote:
>> The feature of color zero pages isn't enabled on arm64, meaning all
>> read-only (anonymous) VM areas are backed up by same zero page. It
>> leads pressure to L1 (data) cache on reading data from them. This
>> tries to enable color zero pages.
>>
>> PATCH[1/2] decouples the zero PGD table from zero page
>> PATCH[2/2] allocates the needed zero pages according to L1 cache size
> 
> To save you (and potential reviewers) some time, please include in the
> cover letter details of a realistic workload/benchmark that is improved
> by this patchset, backed by numbers. Just because it's doable and the
> patches aren't too complex is not a good enough reason for merging.
> 

Sure, Please ignore this (v2) series for now. I'll try to provide
performance data in v3 even I'm not positive about that because
it depends on CPU's L1 dCache size :)

Cheers,
Gavin