From patchwork Mon Sep 28 08:34:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 11803141 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1D63C1580 for ; Mon, 28 Sep 2020 08:36:06 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D68F5207C4 for ; Mon, 28 Sep 2020 08:36:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="FXoPJxVX"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=ti.com header.i=@ti.com header.b="vZTUXFKv" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D68F5207C4 Authentication-Results: mail.kernel.org; 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Mon, 28 Sep 2020 03:34:19 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 28 Sep 2020 03:34:16 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 28 Sep 2020 03:34:16 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 08S8YEaR065485; Mon, 28 Sep 2020 03:34:14 -0500 From: Peter Ujfalusi To: , , , Subject: [PATCH 00/11] firmware/soc: ti_sci, ringacc/inta: Preparation for AM64 DMA support Date: Mon, 28 Sep 2020 11:34:18 +0300 Message-ID: <20200928083429.17390-1-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200928_043421_502066_5A93EFBD X-CRM114-Status: GOOD ( 14.61 ) X-Spam-Score: -3.2 (---) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-3.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [198.47.19.142 listed in list.dnswl.org] 0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [198.47.19.142 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders -0.7 DKIMWL_WL_HIGH DKIMwl.org - High trust sender X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: grygorii.strashko@ti.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Hi, The series prepares the ti_sci, ringacc, inta to support the new DMAs introduced with AM64. Separate series has been sent for the inta irqchip driver: https://lore.kernel.org/lkml/20200928063930.12012-1-peter.ujfalusi@ti.com/ Patches for the DMA support will be based on this series due to build and feature dependencies. To support the new DMSS we need to change the ti_sci ring config API in order to be able to support the new parameters needed in the future. We also need to add support for the second range in RM as along with the AM64 support, the resource allocation is going to change for existing SoC which used only the first range for resource allocation. The tx_tdtype support has been also missing from ti_sci for a long time and the AM64 specific extended_ch_type depends on the existence of it in the message struct. Santosh: if you plan to take this series for 5.11, then can you create an immutable branch which I can refer to Vinod for the DMA patches I'm going to send soon. Regards, Peter --- Peter Ujfalusi (11): firmware: ti_sci: rm: Add support for tx_tdtype parameter for tx channel firmware: ti_sci: Use struct ti_sci_resource_desc in get_range ops firmware: ti_sci: rm: Add support for second resource range soc: ti: ti_sci_inta_msi: Add support for second range in resource ranges firmware: ti_sci: rm: Add support for extended_ch_type for tx channel firmware: ti_sci: rm: Remove ring_get_config support firmware: ti_sci: rm: Add new ops for ring configuration soc: ti: k3-ringacc: Use the ti_sci set_cfg callback for ring configuration firmware: ti_sci: rm: Remove unused config() from ti_sci_rm_ringacc_ops soc: ti: k3-ringacc: Use correct device for allocation in RING mode soc: ti: k3-socinfo: Add entry for AM64 SoC family drivers/firmware/ti_sci.c | 213 ++++++++----------------- drivers/firmware/ti_sci.h | 72 +++------ drivers/soc/ti/k3-ringacc.c | 93 +++++------ drivers/soc/ti/k3-socinfo.c | 1 + drivers/soc/ti/ti_sci_inta_msi.c | 12 ++ include/linux/soc/ti/k3-ringacc.h | 5 + include/linux/soc/ti/ti_sci_protocol.h | 85 ++++++---- 7 files changed, 212 insertions(+), 269 deletions(-)