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dkim=none (message not signed) header.d=none;kernel.dk; dmarc=none action=none header.from=voleatech.de; Received: from AM8PR05MB7251.eurprd05.prod.outlook.com (2603:10a6:20b:1d4::23) by AM0PR0502MB4018.eurprd05.prod.outlook.com (2603:10a6:208:b::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3455.21; Wed, 7 Oct 2020 15:45:57 +0000 Received: from AM8PR05MB7251.eurprd05.prod.outlook.com ([fe80::f132:2cc:34f2:5e4]) by AM8PR05MB7251.eurprd05.prod.outlook.com ([fe80::f132:2cc:34f2:5e4%7]) with mapi id 15.20.3433.045; Wed, 7 Oct 2020 15:45:57 +0000 From: sven.auhagen@voleatech.de To: axboe@kernel.dk, hdegoede@redhat.com, robh+dt@kernel.org, tglx@linutronix.de, maz@kernel.org, gregory.clement@bootlin.com Subject: [PATCH 0/7] Armada8k enable per-port SATA interrupts and drop a hack in the IRQ subsystem Date: Wed, 7 Oct 2020 17:45:47 +0200 Message-Id: <20201007154554.66650-1-sven.auhagen@voleatech.de> X-Mailer: git-send-email 2.24.3 (Apple Git-128) X-Originating-IP: [109.193.235.168] X-ClientProxiedBy: AM0PR04CA0047.eurprd04.prod.outlook.com (2603:10a6:208:1::24) To AM8PR05MB7251.eurprd05.prod.outlook.com (2603:10a6:20b:1d4::23) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from svensmacbookair.sven.lan (109.193.235.168) by AM0PR04CA0047.eurprd04.prod.outlook.com (2603:10a6:208:1::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3455.21 via Frontend Transport; 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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: KZdSsYvQ3Dz/bPCGCSHCerQ4fDIZes6gP08/q7gRhliBTd2NmyxdazW2rFFQroBM43z94+k4ez6RyQmGadK1jKA/TDjTdfjhxhfoZR5G3HrEUwrWwkLJBqjIzSZ/zPyGf8KZyDObsv00GgKWxCTH9I2bMEGyxBa+rwjDL+yPbssa/G5UK2hCGfORkcfNTF4BQX+LyxxoG3TNbsWutq6qXXuINb566SGaaBjwWI+exz5LwYa80c46kag/5U6r4FqlECDtIIRstywUcpp7uqufGfEboVhweUppQiLEmG/t7w8+M1o97zzudw0BwpFAo8Shg3mxGbTmdtUO8BQy95Q37tUx5K/Z/YIqlBDIUL/u6LnrWa4/fjVjQug++ZnLC+ECTuewuVDgLKINuaq3L3aaTLQ0sfq0rzPDsPZ99eEXAYqyy0zZWgyIsCMTdzGS1daNDSQe5DB+LFph/IuF1WW1oYR2wjSkQz6Oc767dM2lw3D95LoPwuh44kdHZRYRTYW0t7olUxiPoZ4U26lqOt4fUP294Ajqc0XGSbXT3ahWisjI2sechCnd/7Si9f2Q0c5///1Wb2UhkIbK0P1nrPvxHg4P1LKhnyFzbR3OnqtD7T/Ed/SiF+16OkmcOyBYW1BddYx69+Dz7/E9M0VwNGA8PA== X-OriginatorOrg: voleatech.de X-MS-Exchange-CrossTenant-Network-Message-Id: 7c43fa48-84a4-44b5-57e8-08d86ad814da X-MS-Exchange-CrossTenant-AuthSource: AM8PR05MB7251.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2020 15:45:57.3954 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b82a99f6-7981-4a72-9534-4d35298f847b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ZtccK/TR3h34pgULO45sIuOACA4E/J3m06Q7pYbwTjf3R+8tr2fRwjz4SnVrj53Gt5tjsqswv2/IqpPnZIG15SgjcuLiLA5YMyBFNrn72WQ= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR0502MB4018 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201007_114602_479625_F231B713 X-CRM114-Status: GOOD ( 14.18 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [40.107.8.125 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [40.107.8.125 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 MSGID_FROM_MTA_HEADER Message-Id was added by a relay X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: andrew@lunn.ch, jason@lakedaemon.net, devicetree@vger.kernel.org, antoine.tenart@bootlin.com, viresh.kumar@linaro.org, rjw@rjwysocki.net, maxime.chevallier@bootlin.com, linux-ide@vger.kernel.org, thomas.petazzoni@bootlin.com, miquel.raynal@bootlin.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Sven Auhagen Hello, I am resubmitting this patch series since I did not get a feedback the past 8 weeks. There were already 4 versions of this series from Miquèl. I talked to Miquèl and I fixed up the last comments from v4. I am looking for feedback if this patch series is now ready to be merged and what should be further changed. Here is the original cover letter: Some time ago, when the initial support for Armada CP110 was contributed, the SATA core was not able to handle per-port interrupts. Despite the hardware reality, the device tree only represents one main interrupt for the two ports. Having both SATA ports enabled at the same time has been achieved by a hack in the ICU driver(1) that faked the use of the two interrupts, no matter which SATA port was in use. Now that the SATA core is ready to handle more than one interrupt, this series adds support for it in the libahci_platform code. The CP110 device tree must be updated to reflect the two SATA ports available and their respective interrupts. To do not break DT backward compatibility, the ahci_platform driver now embeds a special quirk which checks if the DT is valid (only for A8k compatible) and, if needed, creates the two missing sub-nodes, and assign them the relevant "reg" and "interrupts" properties, before removing the main SATA node "interrupts" one. (1) The ICU is an irqchip aggregating the CP110 (south-bridge) interrupts into MSIs for the AP806 (north-bridge). Best Sven Miquel Raynal (5): ata: ahci: mvebu: Rename a platform data flag ata: ahci: mvebu: Support A8k compatible irqchip/irq-mvebu-icu: Remove the double SATA ports interrupt hack dt-bindings: ata: Update ahci bindings with possible per-port interrupts dt-bindings: ata: Update ahci_mvebu bindings Sven Auhagen (2): ata: ahci: mvebu: Add support for A8k legacy DT bindings arm64: dts: marvell: armada-cp110: Switch to per-port SATA interrupts .../devicetree/bindings/ata/ahci-platform.txt | 7 + arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 6 +- drivers/ata/ahci.h | 3 + drivers/ata/ahci_mvebu.c | 254 +++++++++++++++++- drivers/ata/libahci.c | 3 +- drivers/ata/libahci_platform.c | 3 + drivers/irqchip/irq-mvebu-icu.c | 18 -- include/linux/ahci_platform.h | 1 + 8 files changed, 265 insertions(+), 30 deletions(-)