| Message ID | 20210122115257.2502526-1-jean-philippe@linaro.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | iommu/arm-smmu-v3: TLB invalidation for SVA | expand |
On Fri, 22 Jan 2021 12:52:55 +0100 Jean-Philippe Brucker <jean-philippe@linaro.org> wrote: > To support sharing page tables with the CPU, the SMMU can participate in > Broadcast TLB Maintenance (BTM), where TLB invalidate instructions from > the CPU are received by the SMMU. For platforms that do no implement BTM > [1], it is still possible to use SVA, by sending all TLB invalidations > through the command queue. Patch 2 implements this. > > This series also enables SVA for platforms that do support BTM, as an > intermediate step because properly supporting BTM requires cooperating > with KVM to allocate VMIDs [2]. With BTM enabled, the SMMU applies > broadcast invalidations by VMID to any matching TLB entry, because there > is no distinction between private and shared VMIDs like there is for > ASIDs. Therefore a stage-2 domain will need a VMID that doesn't conflict > with one allocated by KVM (or use the one from the corresponding VM, > pinned). > > These patches, along with the IOPF series [3] and the quirks [4], enable > SVA for the hisi accelerator that's already supported upstream. My quick > performance comparison between BTM and !BTM on that platform were > inconclusive. Doing invalidations via cmdq seemed to slightly reduce > performance of some heavy compression jobs, but there was too much noise > and not enough invalidations in my tests. > > This series does not depend on the IOPF one [3]. > > [1] https://lore.kernel.org/linux-iommu/BY5PR12MB37641E84D516054387FEE330B3CC0@BY5PR12MB3764.namprd12.prod.outlook.com/ > [2] https://lore.kernel.org/linux-iommu/20200522101755.GA3453945@myrica/ > [3] https://lore.kernel.org/linux-iommu/20210121123623.2060416-1-jean-philippe@linaro.org/ > [4] https://lore.kernel.org/linux-pci/1610960316-28935-1-git-send-email-zhangfei.gao@linaro.org/ Whole series looks good to me so FWIW Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Will be very nice to have mainline support for SVA with those accelerators :) > > Jean-Philippe Brucker (3): > iommu/arm-smmu-v3: Split arm_smmu_tlb_inv_range() > iommu/arm-smmu-v3: Make BTM optional for SVA > iommu/arm-smmu-v3: Add support for VHE > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 6 + > .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 14 ++- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 104 ++++++++++++------ > 3 files changed, 89 insertions(+), 35 deletions(-) >