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Mon, 22 Feb 2021 05:40:34 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 22 Feb 2021 05:40:34 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 22 Feb 2021 05:40:34 -0600 Received: from a0393678-ssd.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 11MBeVjm105473; Mon, 22 Feb 2021 05:40:31 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Bjorn Helgaas , Rob Herring , Tom Joseph , Lorenzo Pieralisi Subject: [PATCH v3 0/4] AM64: Add PCIe bindings and driver support Date: Mon, 22 Feb 2021 17:10:26 +0530 Message-ID: <20210222114030.26445-1-kishon@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210222_064042_772904_B077CCC0 X-CRM114-Status: GOOD ( 12.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org AM64 uses the same PCIe controller as in J7200, however AM642 EVM doesn't have a clock generator (unlike J7200 base board). Here the clock from the SERDES has to be routed to the PCIE connector. This series provides an option for the pci-j721e.c driver to drive reference clock output to the connector. v1 of the patch series can be found @ [1] v2 of the patch series can be found @ [2] Changes from v2: *) Fix DT binding documentation suggested by Rob Changes from v1: *) Fixed missing initialization of "ret" variable in the error path. [1] -> http://lore.kernel.org/r/20201224115658.2795-1-kishon@ti.com [2] -> https://lore.kernel.org/r/20210104124103.30930-1-kishon@ti.com Kishon Vijay Abraham I (4): dt-bindings: PCI: ti,j721e: Add binding to represent refclk to the connector dt-bindings: PCI: ti,j721e: Add host mode dt-bindings for TI's AM64 SoC dt-bindings: PCI: ti,j721e: Add endpoint mode dt-bindings for TI's AM64 SoC PCI: j721e: Add support to provide refclk to PCIe connector .../bindings/pci/ti,j721e-pci-ep.yaml | 9 ++++---- .../bindings/pci/ti,j721e-pci-host.yaml | 19 +++++++++++------ drivers/pci/controller/cadence/pci-j721e.c | 21 ++++++++++++++++++- 3 files changed, 38 insertions(+), 11 deletions(-)