From patchwork Thu Mar 25 02:51:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Lu X-Patchwork-Id: 12162753 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49FB8C433C1 for ; Thu, 25 Mar 2021 02:54:24 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E7796619FB for ; Thu, 25 Mar 2021 02:54:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E7796619FB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=l6Uf1YYp/yCSP3N70tdtjlhUjJKV+gWAGMfC5D5Wvu0=; b=hJeE9oS8tXG1jv/dM269IK30RY v0r2ypKpkSig1E9Rp6Ez5fUvPP5FyAJlOvZ3GgIoB6VXmWN9qJ4zmsXmVCRDW41cUXLx5S9eeqcZe JBqUY5rj+d7cJe0IqnULqEorqhEFIiNok/dCM2WaeEsTjwNWNYsnmBVFJqCYuqadW4vSkK07IU8LF AQoHtzh8g1wGq8vivZba/KAubxymAegGk7pTJ5C9jvOGAkZA4MdfZfdmpqIrItE1o/Wg6Xtrz2tng OjFc+Kl6St+alEUjZ0l63JbsxDYHySUpKAWdO2eKRyT0Z7eNE3bnIrUEi7ZwPnBDKB5zbBcmTl2E7 DjDFvyiA==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lPG6Z-000VIA-1B; Thu, 25 Mar 2021 02:52:15 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lPG5s-000V9m-7Q; Thu, 25 Mar 2021 02:51:34 +0000 X-UUID: 885d0ecf617b4859b8dae5d792709cc6-20210324 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=ovvxtYk/2nE8eheh97hbjN8ywFQinAxkz5IPvg4DD1g=; b=Mos95STZpFEM6dcNIH8tU6jp9S47ivxN4mlx7x/Hfe3fgeWQNhQWw6L0fF6E2nsY9HH9eR6WhQCgJRP73OAxa1YaNc2fFdtVIR0+NaECYJJ9wafem58i5z9pMOiM+UUwxmQwcrSSwIl3BJ7RbycAxMaS59s4/67V1gZOr1Pq3aY=; X-UUID: 885d0ecf617b4859b8dae5d792709cc6-20210324 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 823318640; Wed, 24 Mar 2021 18:51:20 -0800 Received: from MTKMBS06N2.mediatek.inc (172.21.101.130) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 24 Mar 2021 19:51:18 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs06n2.mediatek.inc (172.21.101.130) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 25 Mar 2021 10:51:14 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 25 Mar 2021 10:51:14 +0800 From: Roger Lu To: Matthias Brugger , Enric Balletbo Serra , Kevin Hilman , Rob Herring , Nicolas Boichat , Stephen Boyd , Philipp Zabel CC: Fan Chen , HenryC Chen , YT Lee , Xiaoqing Liu , Charles Yang , Angus Lin , Mark Rutland , Nishanth Menon , Roger Lu , , , , , , Subject: [PATCH v14 0/7] soc: mediatek: SVS: introduce MTK SVS Date: Thu, 25 Mar 2021 10:51:07 +0800 Message-ID: <20210325025114.25842-1-roger.lu@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-TM-SNTS-SMTP: CCF7532FFE7D28D9056E8883632CDEB3DB4D8251430ED60D9E3CCB9A9AABCD842000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210325_025132_656231_B7FE0DF4 X-CRM114-Status: GOOD ( 11.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org 1. SVS driver uses OPP adjust event in [1] to update OPP table voltage part. 2. SVS driver gets thermal/GPU device by node [2][3] and CPU device by get_cpu_device(). After retrieving subsys device, SVS driver does device_link_add() to make sure probe/suspend callback priority. 3. SVS dts refers to reset controller [4] to help reset SVS HW. #mt8183 SVS related patches [1] https://patchwork.kernel.org/patch/11193513/ [2] https://patchwork.kernel.org/project/linux-mediatek/patch/20201013102358.22588-2-michael.kao@mediatek.com/ [3] https://patchwork.kernel.org/project/linux-mediatek/patch/20200306041345.259332-3-drinkcat@chromium.org/ #mt8192 SVS related patches [1] https://patchwork.kernel.org/patch/11193513/ [2] https://patchwork.kernel.org/project/linux-mediatek/patch/20201223074944.2061-1-michael.kao@mediatek.com/ [3] https://lore.kernel.org/patchwork/patch/1360551/ [4] https://patchwork.kernel.org/project/linux-mediatek/patch/20200817030324.5690-5-crystal.guo@mediatek.com/ changes since v13: - Fix "mtk-svs.yaml: properties:nvmem-cells:maxItems: False schema does not allow 2" - Remove wrong maintainer "Nishanth Menon " - When turn_pt = 0, SVS HIGH bank fills FREQPCT74 / FREQPCT30 with 0 and SVS controller won't run normally. Therefore, we initialize SVS HIGH bank's FREQPCT30 with svsb->freqs_pct[0] to avoid this issue. - Change SVS GPU opp count back from 14 to 16 because GPU DVFS has a better solution Roger Lu (7): [v14,1/7]: dt-bindings: soc: mediatek: add mtk svs dt-bindings [v14,2/7]: arm64: dts: mt8183: add svs device information [v14,3/7]: soc: mediatek: SVS: introduce MTK SVS engine [v14,4/7]: soc: mediatek: SVS: add debug commands [v14,5/7]: dt-bindings: soc: mediatek: add mt8192 svs dt-bindings [v14,6/7]: arm64: dts: mt8192: add svs device information [v14,7/7]: soc: mediatek: SVS: add mt8192 SVS GPU driver .../bindings/soc/mediatek/mtk-svs.yaml | 92 + arch/arm64/boot/dts/mediatek/mt8183.dtsi | 18 + arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 + drivers/soc/mediatek/Kconfig | 10 + drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mtk-svs.c | 2495 +++++++++++++++++ 6 files changed, 2650 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml create mode 100644 drivers/soc/mediatek/mtk-svs.c